table of contents
VHDL(5) | VHDL subset of ASIM/LIP6/CAO-VLSI lab. | VHDL(5) |
NAME¶
ALLIANCE VHDL SubsetORIGIN¶
This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France.DESCRIPTION¶
The ALLIANCE VHDL subset is dedicated to digital synchronous circuits design. The same subset is used for:logic simulation (asimut)
logic synthesis (boom, boog, loon)
functionnal abstraction (yagle)
formal proof (proof)
a structural view may be defined in a file
with a .vst extension (see vst(5)).
a behavioural data flow description may be defined in a file with a .vbe
extension (see vbe(5)).
A typical VHDL model will be made of a hierarcical structural description (a
hierarchy of structural files) and, for each leaf cell, a behavioural
description.
- bit
- the predefined standard bit type ('0' or '1')
- bit_vector
- array of bit
- mux_bit
- a resolved subtype of bit using the mux resolution function. This function checks that only one driver is actually connected to a signal. The effective value of the signal is the value of the active driver. If all drivers are disconnected, the value of the signal is '1' (pull up). A signal of type mux_bit must be declared with the kind bus.
- mux_vector
- array of mux_bit
- wor_bit
- a resolved subtype of bit using the wor resolution function. This function allows a signal be driven by more than one driver. All active drivers have to drive the same value. The effective value of the signal is the value of active drivers. If all drivers are disconnected, the value of the signal is '1' (pull up). A signal of type wor_bit must be declared with the kind bus.
- wor_vector
- array of wor_bit
- reg_bit
- a resolved subtype of bit using the reg resolution function. This function checks that only one driver is actually connected to a signal. The effective value of the signal is the value of the active driver. A signal of type reg_bit must be declared with the kind register (which makes the signal keep its previous value when all drivers are disconnected).
- reg_vector
- array of reg_bit
SEE ALSO¶
vst(5), vbe(5), asimut(1), boom(1), loon(1), boog(1), proof(1)BUG REPORT¶
This tool is under development at the ASIM department of the LIP6 laboratory.October 1, 1997 | ASIM/LIP6 |