table of contents
RING(1) | ALLIANCE USER COMMANDS | RING(1) |
NAME¶
RING - PAD RING routerSYNOPSIS¶
RING source result [ stat ]ORIGIN¶
This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at LIP6 laboratory of Université Pierre et Marie CURIE, in Paris, France.DESCRIPTION¶
source defines two input files:-- the file describing the input netlist
(MBK_IN_LO(1) format).
This file consists in 5 sections: 4 for the pad placement on circuit sides, one
to define the power sypply width (in lambda units).
-- east(), north(), south(), west() define the relative pad order. They use the
pad instance names.
For the north() and south() sections, the instance name declaration are from the
left (first pad) to the right (last pad).
For the east() and west() sections, the instance name declaration are from the
bottom (first pad) to the top (last pad).
Any section may be missing. It means so the revalive side has no pad, however at
least one side must has one pad.
-- the width() section is optional and describes the power (vdd), and ground
(vss) track width.
result defines the output filename.
example: source.al
-- the parameter file: source.rin
- example:
east () # none pad at east side.
north (
p_pck p_i0 p_i1
p_i3)
south (p_vssb p_vddb p_i2)
width (vss 50 vdd 80)
Separators (spaces, tabulations and new line) are allowed between instance
names.
This file contains the layout of the routed
circuit (MBK_OUT_PH(1) format).
RING uses a pad library whose path directory is defined with the MBK_CATA_LIB(1)
environment variable. It also uses a catalog filename which is defined with
the MBK_CATAL_NAME(1) environment variable.
The catalog must contain all the pad model names used in the circuit. The core
model-name must not be present in the catalog.
Part of catalog file:
a2_y C
high_y C
pck_sp C
piot_sp C
pvssick_sp C
pvdde_sp C
pvddi_sp C
[stat] (optional parameter) defines another output file:
example: result.ap
example: *** STATISTIC FILE < result.stat
> ***
Equipotential list :
index| name |lgth A1|lgth A2|area A1|area A2| nb vias_________________________________________________________60 | vss | 9034 | 4408 | 614288| 454024| 1128_________________________________________________________59 | vdd | 7494 | 3968 | 574248| 408704| 1128_________________________________________________________54 | b2_coeur | 2253 | 1899 | 2253| 3798| 4 _________________________________________________________Total length alu1 : 18781 (lambdas)Total length alu2 : 10275 (lambdas)Total area alu1 : 1190789 (lambdas * lambdas)Total area alu2 : 866526 (lambdas * lambdas)Total of vias : 2260
ENVIRONMENT VARIABLES¶
USAGE¶
EXAMPLE¶
- chip.rin:
# This is a comment: 1 comment per line
north(p_a1 p_a2 p_a3 p_a4)
south(
p_i1 #another comment: the rest of the line
p_i2
p_i3
p_i4)
east(p_b4 p_b3 p_b2 p_b1)
west(p_f1 p_f2 p_f3 p_f4)
width(
vdd 80
vss 80
)
In order to obtain the routed circuit (chipr.ap):
> ring chip chipr
- We want a ring of pads as follow:
+-------------------------------------------------+| |p_a1|p_a2|p_a3|p_a4| ||----+---------------------------------------+----||p_f4| |p_b1||----| +-------+ |----||p_f3| | | |p_b2||----| | CORE | |----||p_f2| | | |p_b3||----| +-------+ |----||p_f1| |p_b4||----+---------------------------------------+----|| |p_i1|p_i2|p_i3|p_i4| |+-------------------------------------------------+
SEE ALSO¶
genlib(1) lvx(1) ocp(1) nero(1) druc(1)DIAGNOSTICS¶
Physical core must have at least one physical connector by side, otherwise it can't place pads correctly, and maybe dump a core file.BUG REPORT¶
This tool is under development at the ASIM department of the LIP6 laboratory.October 1, 1997 | ASIM/LIP6 |