other versions
- jessie-backports 4.9.88-1+deb9u1~bpo8+1
- stretch 4.9.144-3
PCI_SET_CACHELINE_SI(9) | Hardware Interfaces | PCI_SET_CACHELINE_SI(9) |
NAME¶
pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmedSYNOPSIS¶
int
pci_set_cacheline_size(struct pci_dev * dev);
ARGUMENTS¶
devthe PCI device for which MWI is to be enabled
DESCRIPTION¶
Helper function for pci_set_mwi. Originally copied from drivers/net/acenic.c. Copyright 1998-2001 by Jes Sorensen, <jes trained-monkey.org>.RETURN¶
An appropriate -ERRNO error value on error, or zero for success.COPYRIGHT¶
May 2018 | Kernel Hackers Manual 4.9. |