.\" Man page generated from reStructuredText. . .TH CTAGS-LANG-VERILOG 7 "" "5.9.0" "Universal Ctags" .SH NAME ctags-lang-verilog \- The man page about SystemVerilog/Verilog parser for Universal Ctags . .nr rst2man-indent-level 0 . .de1 rstReportMargin \\$1 \\n[an-margin] level \\n[rst2man-indent-level] level margin: \\n[rst2man-indent\\n[rst2man-indent-level]] - \\n[rst2man-indent0] \\n[rst2man-indent1] \\n[rst2man-indent2] .. .de1 INDENT .\" .rstReportMargin pre: . RS \\$1 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin] . nr rst2man-indent-level +1 .\" .rstReportMargin post: .. .de UNINDENT . RE .\" indent \\n[an-margin] .\" old: \\n[rst2man-indent\\n[rst2man-indent-level]] .nr rst2man-indent-level -1 .\" new: \\n[rst2man-indent\\n[rst2man-indent-level]] .in \\n[rst2man-indent\\n[rst2man-indent-level]]u .. .SH SYNOPSIS .nf \fBctags\fP ... [\-\-kinds\-systemverilog=+Q] [\-\-fields\-SystemVerilog=+{parameter}] ... \fBctags\fP ... [\-\-fields\-Verilog=+{parameter}] ... .fi .sp .INDENT 0.0 .INDENT 3.5 .TS center; |l|l|l|. _ T{ Language T} T{ Language ID T} T{ File Mapping T} _ T{ SystemVerilog T} T{ SystemVerilog T} T{ \&.sv, .svh, svi T} _ T{ Verilog T} T{ Verilog T} T{ \&.v T} _ .TE .UNINDENT .UNINDENT .SH DESCRIPTION .sp This man page describes about the SystemVerilog/Verilog parser for Universal Ctags. SystemVerilog parser supports IEEE Std 1800\-2017 keywords. Verilog parser supports IEEE Std 1364\-2005 keywords. .SS Supported Kinds .INDENT 0.0 .INDENT 3.5 .sp .nf .ft C $ ctags \-\-list\-kinds\-full=SystemVerilog #LETTER NAME ENABLED REFONLY NROLES MASTER DESCRIPTION A assert yes no 0 NONE assertions (assert, assume, cover, restrict) C class yes no 0 NONE classes E enum yes no 0 NONE enumerators H checker yes no 0 NONE checkers I interface yes no 0 NONE interfaces K package yes no 0 NONE packages L clocking yes no 0 NONE clocking M modport yes no 0 NONE modports N nettype yes no 0 NONE nettype declarations O constraint yes no 0 NONE constraints P program yes no 0 NONE programs Q prototype no no 0 NONE prototypes (extern, pure) R property yes no 0 NONE properties S struct yes no 0 NONE structs and unions T typedef yes no 0 NONE type declarations V covergroup yes no 0 NONE covergroups b block yes no 0 NONE blocks (begin, fork) c constant yes no 0 NONE constants (define, parameter, specparam, enum values) e event yes no 0 NONE events f function yes no 0 NONE functions i instance yes no 0 NONE instances of module or interface l ifclass yes no 0 NONE interface class m module yes no 0 NONE modules n net yes no 0 NONE net data types p port yes no 0 NONE ports q sequence yes no 0 NONE sequences r register yes no 0 NONE variable data types t task yes no 0 NONE tasks w member yes no 0 NONE struct and union members .ft P .fi .UNINDENT .UNINDENT .sp Note that \fBprototype\fP (\fBQ\fP) is disabled by default. .INDENT 0.0 .INDENT 3.5 .sp .nf .ft C $ ctags \-\-list\-kinds\-full=Verilog #LETTER NAME ENABLED REFONLY NROLES MASTER DESCRIPTION b block yes no 0 NONE blocks (begin, fork) c constant yes no 0 NONE constants (define, parameter, specparam) e event yes no 0 NONE events f function yes no 0 NONE functions i instance yes no 0 NONE instances of module m module yes no 0 NONE modules n net yes no 0 NONE net data types p port yes no 0 NONE ports r register yes no 0 NONE variable data types t task yes no 0 NONE tasks .ft P .fi .UNINDENT .UNINDENT .SS Supported Language Specific Fields .INDENT 0.0 .INDENT 3.5 .sp .nf .ft C $ ctags \-\-list\-fields=Verilog #LETTER NAME ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION \- parameter no Verilog \-\-b no parameter whose value can be overridden. $ ctags \-\-list\-fields=SystemVerilog #LETTER NAME ENABLED LANGUAGE JSTYPE FIXED DESCRIPTION \- parameter no SystemVerilog \-\-b no parameter whose value can be overridden. .ft P .fi .UNINDENT .UNINDENT .SS \fBparameter\fP field .sp If the field \fBparameter\fP is enabled, a field \fBparameter:\fP is added on a parameter whose value can be overridden on an instantiated module, interface, or program. This is useful for a editor plugin or extension to enable auto\-instantiation of modules with parameters which can be overridden. .INDENT 0.0 .INDENT 3.5 .sp .nf .ft C $ ctags ... \-\-fields\-Verilog=+{parameter} ... $ ctags ... \-\-fields\-SystemVerilog=+{parameter} ... .ft P .fi .UNINDENT .UNINDENT .sp On the following source code fields \fBparameter:\fP are added on parameters \fBP*\fP, not on ones \fBL*\fP\&. Note that \fBL4\fP and \fBL6\fP is declared by \fBparameter\fP statement, but fields \fBparameter:\fP are not added, because they cannot be overridden. .sp "input.sv" .INDENT 0.0 .INDENT 3.5 .sp .nf .ft C // compilation unit scope parameter L1 = "synonym for the localparam"; module with_parameter_port_list #( P1, localparam L2 = P1+1, parameter P2) ( /*port list...*/ ); parameter L3 = "synonym for the localparam"; localparam L4 = "localparam"; // ... endmodule module with_empty_parameter_port_list #() ( /*port list...*/ ); parameter L5 = "synonym for the localparam"; localparam L6 = "localparam"; // ... endmodule module no_parameter_port_list ( /*port list...*/ ); parameter P3 = "parameter"; localparam L7 = "localparam"; // ... endmodule .ft P .fi .UNINDENT .UNINDENT .INDENT 0.0 .INDENT 3.5 .sp .nf .ft C $ ctags \-uo \- \-\-fields\-SystemVerilog=+{parameter} input.sv L1 input.sv /^parameter L1 = "synonym for the localparam";$/;" c parameter: with_parameter_port_list input.sv /^module with_parameter_port_list #($/;" m P1 input.sv /^ P1,$/;" c module:with_parameter_port_list parameter: L2 input.sv /^ localparam L2 = P1+1,$/;" c module:with_parameter_port_list P2 input.sv /^ parameter P2)$/;" c module:with_parameter_port_list parameter: L3 input.sv /^ parameter L3 = "synonym for the localparam";$/;" c module:with_parameter_port_list L4 input.sv /^ localparam L4 = "localparam";$/;" c module:with_parameter_port_list with_empty_parameter_port_list input.sv /^module with_empty_parameter_port_list #()$/;" m L5 input.sv /^ parameter L5 = "synonym for the localparam";$/;" c module:with_empty_parameter_port_list L6 input.sv /^ localparam L6 = "localparam";$/;" c module:with_empty_parameter_port_list no_parameter_port_list input.sv /^module no_parameter_port_list$/;" m P3 input.sv /^ parameter P3 = "parameter";$/;" c module:no_parameter_port_list parameter: L7 input.sv /^ localparam L7 = "localparam";$/;" c module:no_parameter_port_list .ft P .fi .UNINDENT .UNINDENT .SS TIPS .sp If you want to map files \fB*.v\fP to SystemVerilog, add \fB\-\-langmap=SystemVerilog:.v\fP option. .SH KNOWN ISSUES .sp See \fI\%https://github.com/universal\-ctags/ctags/issues/2674\fP for more information. .SH SEE ALSO .INDENT 0.0 .IP \(bu 2 ctags(1) .IP \(bu 2 ctags\-client\-tools(7) .IP \(bu 2 .INDENT 2.0 .TP .B Language Reference Manuals (LRM) .INDENT 7.0 .IP \(bu 2 IEEE Standard for SystemVerilog — Unified Hardware Design, Specification, and Verification Language, IEEE Std 1800\-2017, \fI\%https://ieeexplore.ieee.org/document/8299595\fP .IP \(bu 2 IEEE Standard for Verilog Hardware Description Language, IEEE Std 1364\-2005, \fI\%https://ieeexplore.ieee.org/document/1620780\fP .UNINDENT .UNINDENT .UNINDENT .\" Generated by docutils manpage writer. .