.\" -*- mode: troff; coding: utf-8 -*- .\" Automatically generated by Pod::Man 5.01 (Pod::Simple 3.43) .\" .\" Standard preamble: .\" ======================================================================== .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp .. .de Vb \" Begin verbatim text .ft CW .nf .ne \\$1 .. .de Ve \" End verbatim text .ft R .fi .. .\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>. .ie n \{\ . ds C` "" . ds C' "" 'br\} .el\{\ . ds C` . ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. .ie \n(.g .ds Aq \(aq .el .ds Aq ' .\" .\" If the F register is >0, we'll generate index entries on stderr for .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .\" .\" Avoid warning from groff about undefined register 'F'. .de IX .. .nr rF 0 .if \n(.g .if rF .nr rF 1 .if (\n(rF:(\n(.g==0)) \{\ . if \nF \{\ . de IX . tm Index:\\$1\t\\n%\t"\\$2" .. . if !\nF==2 \{\ . nr % 0 . nr F 2 . \} . \} .\} .rr rF .\" ======================================================================== .\" .IX Title "Netlist::ContAssign 3pm" .TH Netlist::ContAssign 3pm 2024-03-07 "perl v5.38.2" "User Contributed Perl Documentation" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l .nh .SH NAME Verilog::Netlist::ContAssign \- ContAssign assignment .SH SYNOPSIS .IX Header "SYNOPSIS" .Vb 1 \& use Verilog::Netlist; \& \& ... \& foreach my $cont ($module\->statements) \& print $cont\->name; .Ve .SH DESCRIPTION .IX Header "DESCRIPTION" A Verilog::Netlist::ContAssign object is created by Verilog::Netlist for every continuous assignment statement in the current module. .SH ACCESSORS .IX Header "ACCESSORS" See also Verilog::Netlist::Subclass for additional accessors and methods. .ie n .IP $self\->keyword 4 .el .IP \f(CW$self\fR\->keyword 4 .IX Item "$self->keyword" Keyword used to declare the assignment. Currently "assign" is the only supported value. .ie n .IP $self\->lhs 4 .el .IP \f(CW$self\fR\->lhs 4 .IX Item "$self->lhs" Left hand side of the assignment. .ie n .IP $self\->module 4 .el .IP \f(CW$self\fR\->module 4 .IX Item "$self->module" Pointer to the module the cell is in. .ie n .IP $self\->netlist 4 .el .IP \f(CW$self\fR\->netlist 4 .IX Item "$self->netlist" Reference to the Verilog::Netlist the cell is under. .ie n .IP $self\->rhs 4 .el .IP \f(CW$self\fR\->rhs 4 .IX Item "$self->rhs" Right hand side of the assignment. .SH "MEMBER FUNCTIONS" .IX Header "MEMBER FUNCTIONS" See also Verilog::Netlist::Subclass for additional accessors and methods. .ie n .IP $self\->dump 4 .el .IP \f(CW$self\fR\->dump 4 .IX Item "$self->dump" Prints debugging information for this cell. .SH DISTRIBUTION .IX Header "DISTRIBUTION" Verilog-Perl is part of the free Verilog EDA software tool suite. The latest version is available from CPAN and from . .PP Copyright 2000\-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. .SH AUTHORS .IX Header "AUTHORS" Wilson Snyder .SH "SEE ALSO" .IX Header "SEE ALSO" Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist