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.TH "mlx5dv_devx_create_eq" "3" "2022-01-12" "mlx5" "mlx5 Programmer\[cq]s Manual"
.hy
.SH NAME
.PP
mlx5dv_devx_create_eq - Create an EQ object
.PP
mlx5dv_devx_destroy_eq - Destroy an EQ object
.SH SYNOPSIS
.IP
.nf
\f[C]
#include <infiniband/mlx5dv.h>

struct mlx5dv_devx_eq *
mlx5dv_devx_create_eq(struct ibv_context *ibctx, const void *in, size_t inlen,
              void *out, size_t outlen);

int mlx5dv_devx_destroy_eq(struct mlx5dv_devx_eq *eq);
\f[R]
.fi
.SH DESCRIPTION
.PP
Create / Destroy an EQ object.
Upon creation, the caller prepares the in/out mail boxes based on the
device specification format; For the input mailbox, caller needs to
prepare all fields except \[lq]eqc.log_page_size\[rq] and the pas list,
which will be set by the driver.
The \[lq]eqc.intr\[rq] field should be used from the output of
mlx5dv_devx_alloc_msi_vector().
.SH ARGUMENTS
.TP
\f[I]ibctx\f[R]
RDMA device context to create the action on.
.TP
\f[I]in\f[R]
A buffer which contains the command\[cq]s input data provided in a
device specification format.
.TP
\f[I]inlen\f[R]
The size of \f[I]in\f[R] buffer in bytes.
.TP
\f[I]out\f[R]
A buffer which contains the command\[cq]s output data according to the
device specification format.
.TP
\f[I]outlen\f[R]
The size of \f[I]out\f[R] buffer in bytes.
.TP
\f[I]eq\f[R]
The EQ object to work on.
.IP
.nf
\f[C]
struct mlx5dv_devx_eq {
    void *vaddr;
};
\f[R]
.fi
.TP
\f[I]vaddr\f[R]
EQ VA that was allocated in the driver for.
.SH NOTES
.PP
mlx5dv_devx_query_eqn() will not support vectors which are used by
mlx5dv_devx_create_eq().
.SH RETURN VALUE
.PP
Upon success \f[I]mlx5dv_devx_create_eq\f[R] will return a new
\f[I]struct mlx5dv_devx_eq\f[R]; On error NULL will be returned and
errno will be set.
.PP
Upon success \f[I]mlx5dv_devx_destroy_eq\f[R] will return 0, on error
errno will be returned.
.PP
If the error value is EREMOTEIO, outbox.status and outbox.syndrome will
contain the command failure details.
.SH SEE ALSO
.PP
\f[I]mlx5dv_devx_alloc_msi_vector(3)\f[R],
\f[I]mlx5dv_devx_query_eqn(3)\f[R]
.SH AUTHOR
.PP
Mark Zhang <markzhang@nvidia.com>