.\" Text automatically generated by txt2man
.TH ICETIME 1 "13 June 2023" "" ""
.SH NAME
\fB
\fBicetime \fP- generate timing estimates
\fB
.RE
\fB
.SH SYNOPSIS
.nf
.fam C

  \fBicetime\fP [\fIOPTIONS\fP] FILE.asc


.fam T
.fi
.fam T
.fi
.SH DESCRIPTION

Generate timing estimates from a textual bitstream file (such as
output from arachne-pnr).
.RE
.PP

.SH OPTIONS

.TP
.B
\fB-p\fP <pcf_file>
Specify PCF file to use (needed for correct IO pin names).
.TP
.B
\fB-P\fP <chip_package>
Specify chip package (needed for correct IO pin names).
.TP
.B
\fB-g\fP <net_index>
Write a graphviz description of the interconnect tree
that includes the given net to 'icetime_graph.dot'.
.TP
.B
\fB-o\fP <output_file>
Write verilog netlist to the named file. Use '-'
for stdout.
.TP
.B
\fB-r\fP <output_file>
Write timing report to the named file (instead
of stdout).
.TP
.B
\fB-d\fP lp1k|hx1k|lp8k|hx8k
Select the device type (default = lp variant).
.TP
.B
\fB-m\fP
Enable max_span_hack for conservative timing estimates.
.TP
.B
\fB-i\fP
Only consider interior timing paths (not to/from IOs).
.TP
.B
\fB-t\fP
Print a timing estimate (based on topological timing
analysis).
.TP
.B
\fB-T\fP <net_name>
Print a timing estimate for the specified net.
.TP
.B
\fB-v\fP
Verbose mode (print all interconnect trees).
.RE
.PP

.SH AUTHOR

This manual page was written by Sebastian Kuzminsky <seb@highlab.com>
for the Debian project (and may be used by others).