.\" -*- mode: troff; coding: utf-8 -*- .\" Automatically generated by Pod::Man 5.01 (Pod::Simple 3.43) .\" .\" Standard preamble: .\" ======================================================================== .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp .. .de Vb \" Begin verbatim text .ft CW .nf .ne \\$1 .. .de Ve \" End verbatim text .ft R .fi .. .\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>. .ie n \{\ . ds C` "" . ds C' "" 'br\} .el\{\ . ds C` . ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. .ie \n(.g .ds Aq \(aq .el .ds Aq ' .\" .\" If the F register is >0, we'll generate index entries on stderr for .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .\" .\" Avoid warning from groff about undefined register 'F'. .de IX .. .nr rF 0 .if \n(.g .if rF .nr rF 1 .if (\n(rF:(\n(.g==0)) \{\ . if \nF \{\ . de IX . tm Index:\\$1\t\\n%\t"\\$2" .. . if !\nF==2 \{\ . nr % 0 . nr F 2 . \} . \} .\} .rr rF .\" ======================================================================== .\" .IX Title "VERILATOR 1" .TH VERILATOR 1 2024-01-13 "perl v5.38.2" "User Contributed Perl Documentation" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l .nh .SH NAME Verilator \- Translate and simulate SystemVerilog code using C++/SystemC .SH SYNOPSIS .IX Header "SYNOPSIS" .Vb 6 \& verilator \-\-help \& verilator \-\-version \& verilator \-\-binary \-j 0 [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] \& verilator \-\-cc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] \& verilator \-\-sc [options] [source_files.v]... [opt_c_files.cpp/c/cc/a/o/so] \& verilator \-\-lint\-only \-Wall [source_files.v]... .Ve .SH DESCRIPTION .IX Header "DESCRIPTION" The "Verilator" package converts all synthesizable, and many behavioral, Verilog and SystemVerilog designs into a C++ or SystemC model that after compiling can be executed. Verilator is not a traditional simulator, but a compiler. .PP For documentation see . .SH "ARGUMENT SUMMARY" .IX Header "ARGUMENT SUMMARY" This is a short summary of the arguments to the "verilator" executable. See for the detailed descriptions of these arguments. .PP .Vb 3 \& Verilog package, module, and top module filenames \& Optional C++ files to compile in \& Optional C++ files to link in \& \& +1364\-1995ext+ Use Verilog 1995 with file extension \& +1364\-2001ext+ Use Verilog 2001 with file extension \& +1364\-2005ext+ Use Verilog 2005 with file extension \& +1800\-2005ext+ Use SystemVerilog 2005 with file extension \& +1800\-2009ext+ Use SystemVerilog 2009 with file extension \& +1800\-2012ext+ Use SystemVerilog 2012 with file extension \& +1800\-2017ext+ Use SystemVerilog 2017 with file extension \& \-\-assert Enable all assertions \& \-\-autoflush Flush streams after all $displays \& \-\-bbox\-sys Blackbox unknown $system calls \& \-\-bbox\-unsup Blackbox unsupported language features \& \-\-binary Build model binary \& \-\-build Build model executable/library after Verilation \& \-\-build\-dep\-bin Override build dependency Verilator binary \& \-\-build\-jobs Parallelism for \-\-build \& \-\-cc Create C++ output \& \-\-cdc Clock domain crossing analysis \& \-CFLAGS C++ compiler arguments for makefile \& \-\-clk Mark specified signal as clock \& \-\-no\-clk Prevent marking specified signal as clock \& \-\-compiler Tune for specified C++ compiler \& \-\-converge\-limit Tune convergence settle time \& \-\-coverage Enable all coverage \& \-\-coverage\-line Enable line coverage \& \-\-coverage\-max\-width Maximum array depth for coverage \& \-\-coverage\-toggle Enable toggle coverage \& \-\-coverage\-underscore Enable coverage of _signals \& \-\-coverage\-user Enable SVL user coverage \& \-D[=] Set preprocessor define \& \-\-debug Enable debugging \& \-\-debug\-check Enable debugging assertions \& \-\-no\-debug\-leak Disable leaking memory in \-\-debug mode \& \-\-debugi Enable debugging at a specified level \& \-\-debugi\- Enable debugging a source file at a level \& \-\-no\-decoration Disable comments and symbol decorations \& \-\-default\-language Default language to parse \& +define+= Set preprocessor define \& \-\-dpi\-hdr\-only Only produce the DPI header file \& \-\-dump\-defines Show preprocessor defines with \-E \& \-\-dump\-dfg Enable dumping DfgGraphs to .dot files \& \-\-dump\-graph Enable dumping V3Graphs to .dot files \& \-\-dump\-tree Enable dumping Ast .tree files \& \-\-dump\-tree\-addrids Use short identifiers instead of addresses \& \-\-dump\- Enable dumping everything in source file \& \-\-dumpi\-dfg Enable dumping DfgGraphs to .dot files at level \& \-\-dumpi\-graph Enable dumping V3Graphs to .dot files at level \& \-\-dumpi\-tree Enable dumping Ast .tree files at level \& \-\-dumpi\- Enable dumping everything in source file at level \& \-E Preprocess, but do not compile \& \-\-error\-limit Abort after this number of errors \& \-\-exe Link to create executable \& \-\-expand\-limit Set expand optimization limit \& \-F Parse arguments from a file, relatively \& \-f Parse arguments from a file \& \-FI Force include of a file \& \-\-flatten Force inlining of all modules, tasks and functions \& \-fno\- Disable internal optimization stage \& \-G= Overwrite top\-level parameter \& \-\-gate\-stmts Tune gate optimizer depth \& \-\-gdb Run Verilator under GDB interactively \& \-\-gdbbt Run Verilator under GDB for backtrace \& \-\-generate\-key Create random key for \-\-protect\-key \& \-\-getenv Get environment variable with defaults \& \-\-get\-supported Get if feature is supported \& \-\-help Display this help \& \-\-hierarchical Enable hierarchical Verilation \& \-I Directory to search for includes \& \-\-if\-depth Tune IFDEPTH warning \& +incdir+ Directory to search for includes \& \-\-inline\-mult Tune module inlining \& \-\-instr\-count\-dpi Assumed dynamic instruction count of DPI imports \& \-j Parallelism for \-\-build\-jobs/\-\-verilate\-jobs \& \-\-l2\-name Verilog scope name of the top module \& \-\-language Default language standard to parse \& \-LDFLAGS Linker pre\-object arguments for makefile \& \-\-lib\-create Create a DPI library \& +libext++[ext]... Extensions for finding modules \& \-\-lint\-only Lint, but do not make output \& \-\-make Generate scripts for specified build tool \& \-MAKEFLAGS Arguments to pass to make during \-\-build \& \-\-main Generate C++ main() file \& \-\-main\-top\-name Specify top name passed to Verilated model in generated C++ main \& \-\-max\-num\-width Maximum number width (default: 64K) \& \-\-Mdir Name of output object directory \& \-\-MMD Create .d dependency files \& \-\-mod\-prefix Name to prepend to lower classes \& \-\-MP Create phony dependency targets \& +notimingchecks Ignored \& \-O0 Disable optimizations \& \-O3 High\-performance optimizations \& \-O Selectable optimizations \& \-o Name of final executable \& \-\-no\-order\-clock\-delay Disable ordering clock enable assignments \& \-\-output\-split Split .cpp files into pieces \& \-\-output\-split\-cfuncs Split model functions \& \-\-output\-split\-ctrace Split tracing functions \& \-P Disable line numbers and blanks with \-E \& \-\-pins\-bv Specify types for top\-level ports \& \-\-pins\-sc\-biguint Specify types for top\-level ports \& \-\-pins\-sc\-uint Specify types for top\-level ports \& \-\-pins\-uint8 Specify types for top\-level ports \& \-\-no\-pins64 Don\*(Aqt use uint64_t\*(Aqs for 33\-64 bit sigs \& \-\-pipe\-filter Filter all input through a script \& \-\-pp\-comments Show preprocessor comments with \-E \& \-\-prefix Name of top\-level class \& \-\-private Debugging; see docs \& \-\-prof\-c Compile C++ code with profiling \& \-\-prof\-cfuncs Name functions for profiling \& \-\-prof\-exec Enable generating execution profile for gantt chart \& \-\-prof\-pgo Enable generating profiling data for PGO \& \-\-protect\-ids Hash identifier names for obscurity \& \-\-protect\-key Key for symbol protection \& \-\-protect\-lib Create a DPI protected library \& \-\-public Debugging; see docs \& \-\-public\-params Mark all parameters as public_flat \& \-\-public\-flat\-rw Mark all variables, etc as public_flat_rw \& \-pvalue+= Overwrite toplevel parameter \& \-\-quiet\-exit Don\*(Aqt print the command on failure \& \-\-relative\-includes Resolve includes relative to current file \& \-\-reloop\-limit Minimum iterations for forming loops \& \-\-report\-unoptflat Extra diagnostics for UNOPTFLAT \& \-\-rr Run Verilator and record with rr \& \-\-savable Enable model save\-restore \& \-\-sc Create SystemC output \& \-\-no\-skip\-identical Disable skipping identical output \& \-\-stats Create statistics file \& \-\-stats\-vars Provide statistics on variables \& \-\-no\-std Prevent parsing standard library \& \-\-structs\-packed Convert all unpacked structures to packed structures \& \-sv Enable SystemVerilog parsing \& +systemverilogext+ Synonym for +1800\-2017ext+ \& \-\-threads Enable multithreading \& \-\-threads\-dpi Enable multithreaded DPI \& \-\-threads\-max\-mtasks Tune maximum mtask partitioning \& \-\-timing Enable timing support \& \-\-no\-timing Disable timing support \& \-\-timescale Sets default timescale \& \-\-timescale\-override Overrides all timescales \& \-\-top Alias of \-\-top\-module \& \-\-top\-module Name of top\-level input module \& \-\-trace Enable waveform creation \& \-\-trace\-coverage Enable tracing of coverage \& \-\-trace\-depth Depth of tracing \& \-\-trace\-fst Enable FST waveform creation \& \-\-trace\-max\-array Maximum bit width for tracing \& \-\-trace\-max\-width Maximum array depth for tracing \& \-\-trace\-params Enable tracing of parameters \& \-\-trace\-structs Enable tracing structure names \& \-\-trace\-threads Enable FST waveform creation on separate threads \& \-\-no\-trace\-top Do not emit traces for signals in the top module generated by verilator \& \-\-trace\-underscore Enable tracing of _signals \& \-U Undefine preprocessor define \& \-\-no\-unlimited\-stack Don\*(Aqt disable stack size limit \& \-\-unroll\-count Tune maximum loop iterations \& \-\-unroll\-stmts Tune maximum loop body size \& \-\-unused\-regexp Tune UNUSED lint signals \& \-V Verbose version and config \& \-v Verilog library \& \-\-verilate\-jobs Job threads for Verilation stage \& \-\-no\-verilate Skip Verilation and just compile previously Verilated code \& +verilog1995ext+ Synonym for +1364\-1995ext+ \& +verilog2001ext+ Synonym for +1364\-2001ext+ \& \-\-version Displays program version and exits \& \-\-vpi Enable VPI compiles \& \-\-waiver\-output Create a waiver file based on the linter warnings \& \-Wall Enable all style warnings \& \-Werror\- Convert warnings to errors \& \-Wfuture\- Disable unknown message warnings \& \-Wno\- Disable warning \& \-Wno\-context Disable source context on warnings \& \-Wno\-fatal Disable fatal exit on warnings \& \-Wno\-lint Disable all lint warnings \& \-Wno\-style Disable all style warnings \& \-Wpedantic Warn on compliance\-test issues \& \-Wwarn\- Enable specified warning message \& \-Wwarn\-lint Enable lint warning message \& \-Wwarn\-style Enable style warning message \& \-\-x\-assign Assign non\-initial Xs to this value \& \-\-x\-initial Assign initial Xs to this value \& \-\-x\-initial\-edge Enable initial X\->0 and X\->1 edge triggers \& \-\-xml\-only Create XML parser output \& \-\-xml\-output XML output filename \& \-y Directory to search for modules .Ve .PP This is a short summary of the simulation runtime arguments, i.e. for the final Verilated simulation runtime models. See for the detailed description of these arguments. .PP .Vb 10 \& +verilator+debug Enable debugging \& +verilator+debugi+ Enable debugging at a level \& +verilator+error+limit+ Set error limit \& +verilator+help Display help \& +verilator+noassert Disable assert checking \& +verilator+prof+exec+file+ Set execution profile filename \& +verilator+prof+exec+start+ Set execution profile starting point \& +verilator+prof+exec+window+ Set execution profile duration \& +verilator+prof+vlt+file+ Set PGO profile filename \& +verilator+rand+reset+ Set random reset technique \& +verilator+seed+ Set random seed \& +verilator+V Verbose version and config \& +verilator+version Show version and exit .Ve .SH DISTRIBUTION .IX Header "DISTRIBUTION" The latest version is available from . .PP Copyright 2003\-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. .PP All Verilog and C++/SystemC code quoted within this documentation file are released as Creative Commons Public Domain (CC0). Many example files and test files are likewise released under CC0 into effectively the Public Domain as described in the files themselves. .SH "SEE ALSO" .IX Header "SEE ALSO" verilator_coverage, verilator_gantt, verilator_profcfunc, make, .PP "verilator \-\-help" which is the source for this document, .PP and for detailed documentation.