'\" t .\" Title: struct irq_chip_generic .\" Author: .\" Generator: DocBook XSL Stylesheets v1.79.1 .\" Date: January 2017 .\" Manual: Structures .\" Source: Kernel Hackers Manual 4.8.15 .\" Language: English .\" .TH "STRUCT IRQ_CHIP_GENE" "9" "January 2017" "Kernel Hackers Manual 4\&.8\&." "Structures" .\" ----------------------------------------------------------------- .\" * Define some portability stuff .\" ----------------------------------------------------------------- .\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .\" http://bugs.debian.org/507673 .\" http://lists.gnu.org/archive/html/groff/2009-02/msg00013.html .\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .ie \n(.g .ds Aq \(aq .el .ds Aq ' .\" ----------------------------------------------------------------- .\" * set default formatting .\" ----------------------------------------------------------------- .\" disable hyphenation .nh .\" disable justification (adjust text to left margin only) .ad l .\" ----------------------------------------------------------------- .\" * MAIN CONTENT STARTS HERE * .\" ----------------------------------------------------------------- .SH "NAME" struct_irq_chip_generic \- Generic irq chip data structure .SH "SYNOPSIS" .sp .nf struct irq_chip_generic { raw_spinlock_t lock; void __iomem * reg_base; u32 (* reg_readl) (void __iomem *addr); void (* reg_writel) (u32 val, void __iomem *addr); void (* suspend) (struct irq_chip_generic *gc); void (* resume) (struct irq_chip_generic *gc); unsigned int irq_base; unsigned int irq_cnt; u32 mask_cache; u32 type_cache; u32 polarity_cache; u32 wake_enabled; u32 wake_active; unsigned int num_ct; void * private; unsigned long installed; unsigned long unused; struct irq_domain * domain; struct list_head list; struct irq_chip_type chip_types[0]; }; .fi .SH "MEMBERS" .PP lock .RS 4 Lock to protect register and cache data access .RE .PP reg_base .RS 4 Register base address (virtual) .RE .PP reg_readl .RS 4 Alternate I/O accessor (defaults to readl if NULL) .RE .PP reg_writel .RS 4 Alternate I/O accessor (defaults to writel if NULL) .RE .PP suspend .RS 4 Function called from core code on suspend once per chip; can be useful instead of irq_chip::suspend to handle chip details even when no interrupts are in use .RE .PP resume .RS 4 Function called from core code on resume once per chip; can be useful instead of irq_chip::suspend to handle chip details even when no interrupts are in use .RE .PP irq_base .RS 4 Interrupt base nr for this chip .RE .PP irq_cnt .RS 4 Number of interrupts handled by this chip .RE .PP mask_cache .RS 4 Cached mask register shared between all chip types .RE .PP type_cache .RS 4 Cached type register .RE .PP polarity_cache .RS 4 Cached polarity register .RE .PP wake_enabled .RS 4 Interrupt can wakeup from suspend .RE .PP wake_active .RS 4 Interrupt is marked as an wakeup from suspend source .RE .PP num_ct .RS 4 Number of available irq_chip_type instances (usually 1) .RE .PP private .RS 4 Private data for non generic chip callbacks .RE .PP installed .RS 4 bitfield to denote installed interrupts .RE .PP unused .RS 4 bitfield to denote unused interrupts .RE .PP domain .RS 4 irq domain pointer .RE .PP list .RS 4 List head for keeping track of instances .RE .PP chip_types[0] .RS 4 Array of interrupt irq_chip_types .RE .SH "DESCRIPTION" .PP Note, that irq_chip_generic can have multiple irq_chip_type implementations which can be associated to a particular irq line of an irq_chip_generic instance\&. That allows to share and protect state in an irq_chip_generic instance when we need to implement different flow mechanisms (level/edge) for it\&. .SH "AUTHORS" .PP \fBThomas Gleixner\fR <\&tglx@linutronix.de\&> .RS 4 Author. .RE .PP \fBIngo Molnar\fR <\&mingo@elte.hu\&> .RS 4 Author. .RE .SH "COPYRIGHT" .br