'\" t .\" Title: irq_gc_mask_set_bit .\" Author: .\" Generator: DocBook XSL Stylesheets v1.79.1 .\" Date: January 2017 .\" Manual: Generic interrupt chip .\" Source: Kernel Hackers Manual 4.8.15 .\" Language: English .\" .TH "IRQ_GC_MASK_SET_BIT" "9" "January 2017" "Kernel Hackers Manual 4\&.8\&." "Generic interrupt chip" .\" ----------------------------------------------------------------- .\" * Define some portability stuff .\" ----------------------------------------------------------------- .\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .\" http://bugs.debian.org/507673 .\" http://lists.gnu.org/archive/html/groff/2009-02/msg00013.html .\" ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .ie \n(.g .ds Aq \(aq .el .ds Aq ' .\" ----------------------------------------------------------------- .\" * set default formatting .\" ----------------------------------------------------------------- .\" disable hyphenation .nh .\" disable justification (adjust text to left margin only) .ad l .\" ----------------------------------------------------------------- .\" * MAIN CONTENT STARTS HERE * .\" ----------------------------------------------------------------- .SH "NAME" irq_gc_mask_set_bit \- Mask chip via setting bit in mask register .SH "SYNOPSIS" .HP \w'void\ irq_gc_mask_set_bit('u .BI "void irq_gc_mask_set_bit(struct\ irq_data\ *\ " "d" ");" .SH "ARGUMENTS" .PP \fId\fR .RS 4 irq_data .RE .SH "DESCRIPTION" .PP Chip has a single mask register\&. Values of this register are cached and protected by gc\->lock .SH "AUTHORS" .PP \fBThomas Gleixner\fR <\&tglx@linutronix.de\&> .RS 4 Author. .RE .PP \fBIngo Molnar\fR <\&mingo@elte.hu\&> .RS 4 Author. .RE .SH "COPYRIGHT" .br