.\" -*- mode: troff; coding: utf-8 -*- .\" Automatically generated by Pod::Man 5.01 (Pod::Simple 3.43) .\" .\" Standard preamble: .\" ======================================================================== .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp .. .de Vb \" Begin verbatim text .ft CW .nf .ne \\$1 .. .de Ve \" End verbatim text .ft R .fi .. .\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>. .ie n \{\ . ds C` "" . ds C' "" 'br\} .el\{\ . ds C` . ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. .ie \n(.g .ds Aq \(aq .el .ds Aq ' .\" .\" If the F register is >0, we'll generate index entries on stderr for .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .\" .\" Avoid warning from groff about undefined register 'F'. .de IX .. .nr rF 0 .if \n(.g .if rF .nr rF 1 .if (\n(rF:(\n(.g==0)) \{\ . if \nF \{\ . de IX . tm Index:\\$1\t\\n%\t"\\$2" .. . if !\nF==2 \{\ . nr % 0 . nr F 2 . \} . \} .\} .rr rF .\" ======================================================================== .\" .IX Title "Netlist::Subclass 3pm" .TH Netlist::Subclass 3pm 2024-01-27 "perl v5.38.2" "User Contributed Perl Documentation" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l .nh .SH NAME Verilog::Netlist::Subclass \- Common routines for all classes .SH SYNOPSIS .IX Header "SYNOPSIS" .Vb 3 \& package Verilog::Netlist::Something; \& use Verilog::Netlist::Subclass; \& use base qw(Verilog::Netlist::Subclass); \& \& ... \& \& $self\->info("We\*(Aqre here\en"); \& $self\->warn("Things look bad\en"); \& $self\->error("Things are even worse\en"); \& $self\->exit_if_error(); .Ve .SH DESCRIPTION .IX Header "DESCRIPTION" The Verilog::Netlist::Subclass is used as a base class for all Verilog::Netlist::* structures. It is mainly used so that \f(CW$self\fR\->\fBwarn()\fR and \f(CW$self\fR\->\fBerror()\fR will produce consistent results. .SH "MEMBER FUNCTIONS" .IX Header "MEMBER FUNCTIONS" .ie n .IP $self\->error(\fIText...\fR) 4 .el .IP \f(CW$self\fR\->error(\fIText...\fR) 4 .IX Item "$self->error(Text...)" Print an error in a standard format. .ie n .IP $self\->\fBerrors()\fR 4 .el .IP \f(CW$self\fR\->\fBerrors()\fR 4 .IX Item "$self->errors()" Return number of errors detected. .ie n .IP $self\->\fBexit_if_error()\fR 4 .el .IP \f(CW$self\fR\->\fBexit_if_error()\fR 4 .IX Item "$self->exit_if_error()" Exits the program if any errors were detected. .ie n .IP $self\->\fBfilename()\fR 4 .el .IP \f(CW$self\fR\->\fBfilename()\fR 4 .IX Item "$self->filename()" The filename number the entity was created in. .ie n .IP $self\->info(\fIText...\fR) 4 .el .IP \f(CW$self\fR\->info(\fIText...\fR) 4 .IX Item "$self->info(Text...)" Print a informational in a standard format. .ie n .IP $self\->\fBlineno()\fR 4 .el .IP \f(CW$self\fR\->\fBlineno()\fR 4 .IX Item "$self->lineno()" The line number the entity was created on. .ie n .IP $self\->\fBlogger()\fR 4 .el .IP \f(CW$self\fR\->\fBlogger()\fR 4 .IX Item "$self->logger()" The class to report errors using, generally a Verilog::Netlist::Logger object. .ie n .IP "$self\->userdata(\fIkey\fR) =item $self\->userdata(\fIkey\fR, \fIdata\fR)" 4 .el .IP "\f(CW$self\fR\->userdata(\fIkey\fR) =item \f(CW$self\fR\->userdata(\fIkey\fR, \fIdata\fR)" 4 .IX Item "$self->userdata(key) =item $self->userdata(key, data)" Sets (with two arguments) or retrieves the specified key from an opaque hash. This may be used to store application data on the specified node. .ie n .IP $self\->warn(\fIText...\fR) 4 .el .IP \f(CW$self\fR\->warn(\fIText...\fR) 4 .IX Item "$self->warn(Text...)" Print a warning in a standard format. .ie n .IP $self\->\fBwarnings()\fR 4 .el .IP \f(CW$self\fR\->\fBwarnings()\fR 4 .IX Item "$self->warnings()" Return number of warnings detected. .SH DISTRIBUTION .IX Header "DISTRIBUTION" Verilog-Perl is part of the free Verilog EDA software tool suite. The latest version is available from CPAN and from . .PP Copyright 2000\-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. .SH AUTHORS .IX Header "AUTHORS" Wilson Snyder .SH "SEE ALSO" .IX Header "SEE ALSO" Verilog-Perl, Verilog::Netlist