.\" -*- mode: troff; coding: utf-8 -*- .\" Automatically generated by Pod::Man 5.01 (Pod::Simple 3.43) .\" .\" Standard preamble: .\" ======================================================================== .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp .. .de Vb \" Begin verbatim text .ft CW .nf .ne \\$1 .. .de Ve \" End verbatim text .ft R .fi .. .\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>. .ie n \{\ . ds C` "" . ds C' "" 'br\} .el\{\ . ds C` . ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. .ie \n(.g .ds Aq \(aq .el .ds Aq ' .\" .\" If the F register is >0, we'll generate index entries on stderr for .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .\" .\" Avoid warning from groff about undefined register 'F'. .de IX .. .nr rF 0 .if \n(.g .if rF .nr rF 1 .if (\n(rF:(\n(.g==0)) \{\ . if \nF \{\ . de IX . tm Index:\\$1\t\\n%\t"\\$2" .. . if !\nF==2 \{\ . nr % 0 . nr F 2 . \} . \} .\} .rr rF .\" ======================================================================== .\" .IX Title "Netlist::Port 3pm" .TH Netlist::Port 3pm 2024-01-27 "perl v5.38.2" "User Contributed Perl Documentation" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l .nh .SH NAME Verilog::Netlist::Port \- Port for a Verilog Module .SH SYNOPSIS .IX Header "SYNOPSIS" .Vb 1 \& use Verilog::Netlist; \& \& ... \& my $port = $module\->find_port(\*(Aqpinname\*(Aq); \& print $port\->name; .Ve .SH DESCRIPTION .IX Header "DESCRIPTION" A Verilog::Netlist::Port object is created by Verilog::Netlist::Module for every port connection in the module. .SH ACCESSORS .IX Header "ACCESSORS" See also Verilog::Netlist::Subclass for additional accessors and methods. .ie n .IP $self\->array 4 .el .IP \f(CW$self\fR\->array 4 .IX Item "$self->array" Any array declaration for the port. This only applies to Verilog 1995 style ports which can declare port bits independently from the signal declarations. When using Verilog 2001 style ports, see the matching net declaration's data_type, msb and lsb methods instead, for example \&\f(CW\*(C`$module\-\*(C'\fRfind_net($port\->name)\->data_type>. .ie n .IP $self\->comment 4 .el .IP \f(CW$self\fR\->comment 4 .IX Item "$self->comment" Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained. .ie n .IP $self\->data_type 4 .el .IP \f(CW$self\fR\->data_type 4 .IX Item "$self->data_type" The SystemVerilog data type of the port. .ie n .IP $self\->direction 4 .el .IP \f(CW$self\fR\->direction 4 .IX Item "$self->direction" The direction of the port: "in", "out", or "inout". .ie n .IP $self\->module 4 .el .IP \f(CW$self\fR\->module 4 .IX Item "$self->module" Reference to the Verilog::Netlist::Module the port is in. .ie n .IP $self\->name 4 .el .IP \f(CW$self\fR\->name 4 .IX Item "$self->name" The name of the port. .ie n .IP $self\->net 4 .el .IP \f(CW$self\fR\->net 4 .IX Item "$self->net" Reference to the Verilog::Netlist::Net the port connects to. Only valid after the netlist is linked. .ie n .IP $self\->type 4 .el .IP \f(CW$self\fR\->type 4 .IX Item "$self->type" Approximately an alias of data_type for backward compatibility. Do not use for new applications. .SH "MEMBER FUNCTIONS" .IX Header "MEMBER FUNCTIONS" See also Verilog::Netlist::Subclass for additional accessors and methods. .ie n .IP $self\->dump 4 .el .IP \f(CW$self\fR\->dump 4 .IX Item "$self->dump" Prints debugging information for this port. .SH DISTRIBUTION .IX Header "DISTRIBUTION" Verilog-Perl is part of the free Verilog EDA software tool suite. The latest version is available from CPAN and from . .PP Copyright 2000\-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. .SH AUTHORS .IX Header "AUTHORS" Wilson Snyder .SH "SEE ALSO" .IX Header "SEE ALSO" Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist