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.\"
.IX Title "Netlist::Pin 3pm"
.TH Netlist::Pin 3pm 2024-01-27 "perl v5.38.2" "User Contributed Perl Documentation"
.\" For nroff, turn off justification.  Always turn off hyphenation; it makes
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.nh
.SH NAME
Verilog::Netlist::Pin \- Pin on a Verilog Cell
.SH SYNOPSIS
.IX Header "SYNOPSIS"
.Vb 1
\&  use Verilog::Netlist;
\&
\&  ...
\&  my $pin = $cell\->find_pin(\*(Aqpinname\*(Aq);
\&  print $pin\->name;
.Ve
.SH DESCRIPTION
.IX Header "DESCRIPTION"
A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for
each pin connection on a cell.  A Pin connects a net in the current design
to a port on the instantiated cell's module.
.SH ACCESSORS
.IX Header "ACCESSORS"
See also Verilog::Netlist::Subclass for additional accessors and methods.
.ie n .IP $self\->cell 4
.el .IP \f(CW$self\fR\->cell 4
.IX Item "$self->cell"
Reference to the Verilog::Netlist::Cell the pin is under.
.ie n .IP $self\->comment 4
.el .IP \f(CW$self\fR\->comment 4
.IX Item "$self->comment"
Returns any comments following the definition.  keep_comments=>1 must be
passed to Verilog::Netlist::new for comments to be retained.
.ie n .IP $self\->delete 4
.el .IP \f(CW$self\fR\->delete 4
.IX Item "$self->delete"
Delete the pin from the cell it's under.
.ie n .IP $self\->module 4
.el .IP \f(CW$self\fR\->module 4
.IX Item "$self->module"
Reference to the Verilog::Netlist::Module the pin is in.
.ie n .IP $self\->name 4
.el .IP \f(CW$self\fR\->name 4
.IX Item "$self->name"
The name of the pin.  May have extra characters to make vectors connect,
generally portname is a more readable version.  There may be multiple pins
with the same portname, only one pin has a given name.
.ie n .IP $self\->net 4
.el .IP \f(CW$self\fR\->net 4
.IX Item "$self->net"
Reference to the Verilog::Netlist::Net the pin connects to.  Only valid
after a link.  This function is deprecated; use nets or nets_sorted
instead.
.ie n .IP $self\->nets 4
.el .IP \f(CW$self\fR\->nets 4
.IX Item "$self->nets"
Array of hashes the pin connects to.  Each hash contains a msb, lsb, and
net (a Verilog::Netlist::Net).  Only valid after a link.
.ie n .IP $self\->nets_sorted 4
.el .IP \f(CW$self\fR\->nets_sorted 4
.IX Item "$self->nets_sorted"
Array of sorted hashes the pin connects to.  Each hash contains a msb, lsb,
and net (a Verilog::Netlist::Net).  Only valid after a link.
.ie n .IP $self\->netlist 4
.el .IP \f(CW$self\fR\->netlist 4
.IX Item "$self->netlist"
Reference to the Verilog::Netlist the pin is in.
.ie n .IP $self\->netname 4
.el .IP \f(CW$self\fR\->netname 4
.IX Item "$self->netname"
The net name the pin connects to.  This function is deprecated; use
pinselects instead.
.ie n .IP $self\->pinselects 4
.el .IP \f(CW$self\fR\->pinselects 4
.IX Item "$self->pinselects"
The net names the pins connect to, as an array of Verilog::Netlist::PinSelection elements.
.ie n .IP $self\->portname 4
.el .IP \f(CW$self\fR\->portname 4
.IX Item "$self->portname"
The name of the port connected to.
.ie n .IP $self\->port 4
.el .IP \f(CW$self\fR\->port 4
.IX Item "$self->port"
Reference to the Verilog::Netlist::Port the pin connects to.  Only valid after a link.
.SH "MEMBER FUNCTIONS"
.IX Header "MEMBER FUNCTIONS"
See also Verilog::Netlist::Subclass for additional accessors and methods.
.ie n .IP $self\->lint 4
.el .IP \f(CW$self\fR\->lint 4
.IX Item "$self->lint"
Checks the pin for errors.  Normally called by Verilog::Netlist::lint.
.ie n .IP $self\->dump 4
.el .IP \f(CW$self\fR\->dump 4
.IX Item "$self->dump"
Prints debugging information for this pin.
.SH DISTRIBUTION
.IX Header "DISTRIBUTION"
Verilog-Perl is part of the <https://www.veripool.org/> free Verilog EDA
software tool suite.  The latest version is available from CPAN and from
<https://www.veripool.org/verilog\-perl>.
.PP
Copyright 2000\-2024 by Wilson Snyder.  This package is free software; you
can redistribute it and/or modify it under the terms of either the GNU
Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
.SH AUTHORS
.IX Header "AUTHORS"
Wilson Snyder <wsnyder@wsnyder.org>
.SH "SEE ALSO"
.IX Header "SEE ALSO"
Verilog-Perl,
Verilog::Netlist::Subclass,
Verilog::Netlist,
Verilog::Netlist::PinSelection