.\" -*- mode: troff; coding: utf-8 -*- .\" Automatically generated by Pod::Man 5.01 (Pod::Simple 3.43) .\" .\" Standard preamble: .\" ======================================================================== .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp .. .de Vb \" Begin verbatim text .ft CW .nf .ne \\$1 .. .de Ve \" End verbatim text .ft R .fi .. .\" \*(C` and \*(C' are quotes in nroff, nothing in troff, for use with C<>. .ie n \{\ . ds C` "" . ds C' "" 'br\} .el\{\ . ds C` . ds C' 'br\} .\" .\" Escape single quotes in literal strings from groff's Unicode transform. .ie \n(.g .ds Aq \(aq .el .ds Aq ' .\" .\" If the F register is >0, we'll generate index entries on stderr for .\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .\" .\" Avoid warning from groff about undefined register 'F'. .de IX .. .nr rF 0 .if \n(.g .if rF .nr rF 1 .if (\n(rF:(\n(.g==0)) \{\ . if \nF \{\ . de IX . tm Index:\\$1\t\\n%\t"\\$2" .. . if !\nF==2 \{\ . nr % 0 . nr F 2 . \} . \} .\} .rr rF .\" ======================================================================== .\" .IX Title "Netlist::File 3pm" .TH Netlist::File 3pm 2024-01-27 "perl v5.38.2" "User Contributed Perl Documentation" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l .nh .SH NAME Verilog::Netlist::File \- File containing Verilog code .SH SYNOPSIS .IX Header "SYNOPSIS" .Vb 1 \& use Verilog::Netlist; \& \& my $nl = new Verilog::Netlist; \& my $fileref = $nl\->read_file(filename=>\*(Aqfilename\*(Aq); .Ve .SH DESCRIPTION .IX Header "DESCRIPTION" Verilog::Netlist::File allows Verilog::Netlist objects to be read and written in Verilog format. .SH ACCESSORS .IX Header "ACCESSORS" See also Verilog::Netlist::Subclass for additional accessors and methods. .ie n .IP $self\->basename 4 .el .IP \f(CW$self\fR\->basename 4 .IX Item "$self->basename" The filename of the file with any path and . suffix stripped off. .ie n .IP $self\->name 4 .el .IP \f(CW$self\fR\->name 4 .IX Item "$self->name" The filename of the file. .ie n .IP $self\->preproc 4 .el .IP \f(CW$self\fR\->preproc 4 .IX Item "$self->preproc" The Verilog::Preproc object this file is using. .SH "MEMBER FUNCTIONS" .IX Header "MEMBER FUNCTIONS" See also Verilog::Netlist::Subclass for additional accessors and methods. .ie n .IP $self\->read 4 .el .IP \f(CW$self\fR\->read 4 .IX Item "$self->read" Generally called as \f(CW$netlist\fR\->read_file. Pass a hash of parameters. Reads the filename=> parameter, parsing all instantiations, ports, and signals, and creating Verilog::Netlist::Module structures. .ie n .IP $self\->dump 4 .el .IP \f(CW$self\fR\->dump 4 .IX Item "$self->dump" Prints debugging information for this file. .SH DISTRIBUTION .IX Header "DISTRIBUTION" Verilog-Perl is part of the free Verilog EDA software tool suite. The latest version is available from CPAN and from . .PP Copyright 2000\-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. .SH AUTHORS .IX Header "AUTHORS" Wilson Snyder .SH "SEE ALSO" .IX Header "SEE ALSO" Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist