.\"   $Id: vhdl.5,v 1.3 2002/10/17 16:45:55 xtof Exp $
.\" @(#)vhdl.5 1.0 Jan 28 1993 UPMC ; VUONG H.N.
.TH VHDL 5 "October 1, 1997" "ASIM/LIP6" "VHDL subset of ASIM/LIP6/CAO-VLSI lab."

.SH NAME
.PP
\fBALLIANCE VHDL Subset\fP

.so jessie/alliance/alc_origin.1.en.gz
.SH DESCRIPTION
.PP
The ALLIANCE VHDL subset is dedicated to digital synchronous circuits design.
The same subset is used for:
.RS
logic simulation (asimut)
.br
logic synthesis (boom, boog, loon)
.br
functionnal abstraction (yagle)
.br
formal proof (proof)
.RE

.PP
The ALLIANCE VHDL subset is fully compatible with the IEEE VHDL standard Ref.
1076 (1987). That means that a VHDL description using the ALLIANCE subset can
be simulated with any full-VHDL commercial compiler-simulator.

.PP
Here follows the main restrictions of the ALLIANCE subset.

.PP
The VHDL description of a circuit is made of two seperate parts: the external
view and the internal view.

.PP
The external view defines the name of the circuit and its interface. The
interface of a circuit is a list of ports. Each port is specified by its name,
its mode, its type, its constraint for an array and, its kind.

.PP
The mode of a port depends only on the manner the port is used inside the
circuit (in the internal view of the circuit). If the value of a port is to be
read in the view of the description, the port must be declared with the mode
\fIin\fP. If the value of a port is to be written by the internal view, the
port must be declared with the mode \fIout\fP. If both above conditions are
satisfied the port must be declared with the mode \fIinout\fP.

.PP
Only \fIstructural\fP and \fIbehavioural data flow\fP are supported as internal
view.

.PP
In order to allow automatic translation from structural VHDL to other netlist
formats (EDIF, ALLIANCE, COMPASS, ...) it is not possible to mix behavioural
and structural description. Of course, a circuit, a subcircuit or a cell can
have two different descriptions:
.RS
a structural view may be defined in a file with a .vst extension (see vst(5)).
.br
a behavioural data flow description may be defined in a file with a .vbe
extension (see vbe(5)).
.RE
.PP
A typical VHDL model will be made of a hierarcical structural description (a
hierarchy of structural files) and, for each leaf cell, a behavioural
description.

.PP
In a behavioural description, only concurrent statements (except \fIprocess\fP)
are supported. Up to now, sequential statements are not allowed by the ALLIANCE
VHDL compiler.

.\" .PP
.\" As behavioural descriptions are used for both logic simulation and logic
.\" synthesis, detailed timing information is not needed. That means, within a
.\" concurrent statement no delay can be specified (\fIafter\fP is not supported).

.PP
Timing information can be specified in behavioural descriptions using \fIAfter clauses\fP. However, those delays are currently only used for simulation. \fIAfter clauses\fP are supported but not used for synthesis and formal proof.

.PP
A predefined set of types has been defined (other user defined types are not
supported):
.TP 15
\fBbit\fP
the predefined standard bit type ('0' or '1')
.TP 15
\fBbit_vector\fP
array of bit
.TP 15
\fBmux_bit\fP
a resolved subtype of bit using the \fImux\fP resolution function. This
function checks that only one driver is actually connected to a signal. The
effective value of the signal is the value of the active driver. If all drivers
are disconnected, the value of the signal is '1' (pull up). A signal of type
mux_bit must be declared with the kind \fIbus\fP.
.TP 15
\fBmux_vector\fP
array of mux_bit
.TP 15
\fBwor_bit\fP
a resolved subtype of bit using the \fIwor\fP resolution function. This
function allows a signal be driven by more than one driver. All active drivers
have to drive the same value. The effective value of the signal is the value
of active drivers. If all drivers are disconnected, the value of the signal
is '1' (pull up). A signal of type wor_bit must be declared with the kind
\fIbus\fP.
.TP 15
\fBwor_vector\fP
array of wor_bit
.TP 15
\fBreg_bit\fP
a resolved subtype of bit using the \fIreg\fP resolution function. This
function checks that only one driver is actually connected to a signal. The
effective value of the signal is the value of the active driver. A signal of
type reg_bit must be declared with the kind \fIregister\fP (which makes the
signal keep its previous value when all drivers are disconnected).
.TP 15
\fBreg_vector\fP
array of reg_bit

.PP
In the next ALLIANCE release the VHDL subset will be largely extended
(sequential statements, user defined types) .

.SH SEE ALSO
.PP
vst(5), vbe(5), asimut(1), boom(1), loon(1), boog(1), proof(1)


.so jessie/alliance/alc_bug_report.1.en.gz