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.TH "DPGEN_RF1" "3" "30 July 2004" "ASIM/LIP6" "Alliance - genlib User's Manual"

.SH NAME
DPGEN_RF1, DPGEN_RF1R0 \- Register File Macro-Generator
.SH SYNOPSIS
.sp
\fB#include  <genlib.h>
.sp
void GENLIB_MACRO (DPGEN_RF1, char *\fImodelname\fB, long \fIflags\fB, long \fIN\fB);
.sp
void GENLIB_MACRO (DPGEN_RF1R0, char *\fImodelname\fB, long \fIflags\fB, long \fIN\fB);
\fR
.SH "DESCRIPTION"
.PP
Generate a register file of \fIregNumber\fR words of \fIN\fR bits
whitout decoder named \fImodelname\fR\&. The DPGEN_RF1R0 variant differs
from the DPGEN_RF1 in that the register of address zero is stuck to
zero. You can write into it, it will not change the value. When read,
it will always return zero.
.PP
How it works :
.TP 0.2i
\(bu
datain0 and datain1 : the two write busses. Only one
is used to actually write the register word, it is selected by
the sel signal.
.TP 0.2i
\(bu
sel : when set to \&'0' the datain0 is used to write
the register word, otherwise it will be datain1\&.
.TP 0.2i
\(bu
selr, selw : this register file have no decoder, so
selr have a bus width equal to \fIregNumber\fR\&. One bit for each word.
.SS "TERMINAL NAMES"
.TP 3
1. 
ckok : clock signal (input, 1 bit). 
.TP 3
2. 
sel : select the write bus (input, 1 bit). 
.TP 3
3. 
selr : the decoded read address (input, \fIregNumber\fR bits). 
.TP 3
4. 
selw : the decoded write address (input, \fIregNumber\fR bits). 
.TP 3
5. 
datain0 :  first write bus (input, \fIN\fR bits). 
.TP 3
6. 
datain1 :  second write bus (input, \fIN\fR bits). 
.TP 3
7. 
dataout : read bus (output, \fIN\fR bits). 
.TP 3
8. 
vdd : power. 
.TP 3
9. 
vss : ground. 
.SH "EXAMPLE"
.PP

.nf
GENLIB_MACRO(DPGEN_RF1, "model_rf1x8_32"
                      , F_BEHAV|F_PLACE
                      , 32  /* Words size.      */
                      , 8   /* Number of words. */
                      );

GENLIB_LOINS( "model_rf1x8_32"
            , "instance1_rf1_32"
            , "ckok"
            , "sel"
            , "selr[7:0]"
            , "selw[7:0]"
            , "datain0[31:0]"
            , "datain1[31:0]"
            , "dataout[31:0]"
            , "vdd", "vss", NULL
            );
    
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)