.\" This manpage has been automatically generated by docbook2man .\" from a DocBook document. This tool can be found at: .\" .\" Please send any bug reports, improvements, comments, patches, .\" etc. to Steve Cheng . .TH "DPGEN_FIFO" "3" "30 July 2004" "ASIM/LIP6" "Alliance - genlib User's Manual" .SH NAME DPGEN_FIFO \- FIFO Macro-Generator .SH SYNOPSIS .sp \fB#include .sp void GENLIB_MACRO (DPGEN_FIFO, char *\fImodelname\fB, long \fIflags\fB, long \fIN\fB); \fR .SH "DESCRIPTION" .PP Generate a FIFO of \fIregNumber\fR words of \fIN\fR bits named \fImodelname\fR\&. .PP How it works : .TP 0.2i \(bu datain0 and datain1 : the two write busses. Only one is used to actually write the FIFO, it is selected by the sel signal. .TP 0.2i \(bu sel : when set to \&'0' the datain0 is used to write the register word, otherwise it will be datain1\&. .TP 0.2i \(bu r, rok : set r when a word is requested, rok tells that a word has effectively been popped (rok == not empty). .TP 0.2i \(bu w, wok : set w when a word is pushed, wok tells that the word has effectively been pushed (wok == not full). .SS "TERMINAL NAMES" .TP 3 1. ck : clock signal (input, 1 bit). .TP 3 2. reset : reset signal (input, 1 bit). .TP 3 3. r : read requested (input, 1 bits). .TP 3 4. w : write requested (input, 1 bits). .TP 3 5. rok : read acknowledge (output, 1 bits). .TP 3 6. wok : write acknowledge (output, 1 bits). .TP 3 7. sel : select the write bus (input, 1 bit). .TP 3 8. datain0 : first write bus (input, \fIN\fR bits). .TP 3 9. datain1 : second write bus (input, \fIN\fR bits). .TP 3 10. dataout : read bus (output, \fIN\fR bits). .TP 3 11. vdd : power. .TP 3 12. vss : ground. .SH "EXAMPLE" .PP .nf GENLIB_MACRO(DPGEN_RF1, "model_fifox8_32" , F_BEHAV|F_PLACE , 32 /* Words size. */ , 8 /* Number of words. */ ); GENLIB_LOINS( "model_fifox8_32" , "instance1_fifo1_32" , "ck" , "r" , "w" , "rok" , "wok" , "sel" , "datain0[31:0]" , "datain1[31:0]" , "dataout[31:0]" , "vdd", "vss", NULL ); .fi .SH "SEE ALSO" .PP \fBGENLIB_MACRO\fR(3), \fBgenlib\fR(1)