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.TH "DPGEN_SHIFT" "3" "30 July 2004" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_SHIFT \- Shifter Macro-Generator
.SH SYNOPSIS
.sp
\fB#include
.sp
void GENLIB_MACRO (DPGEN_SHIFT, char *\fImodelname\fB, long \fIflags\fB, long \fIN\fB);
\fR
.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits shifter with name \fImodelname\fR\&.
.PP
How it works :
.TP 0.2i
\(bu
if the op[0] signal is set to \&'1' performs
a right shift, performs a left shift otherwise.
.TP 0.2i
\(bu
if the op[1] signal is set to \&'1' performs
an arithmetic shift (only meaningful in case of a right shift).
.TP 0.2i
\(bu
shamt : specifies the shift amount. The width of this signal
(\fIY\fR) is computed from the operator's width :
Y = ceil(log2(N)) - 1\&.
.SS "TERMINAL NAMES"
.TP 3
1.
op : select the kind of shift (input, 2 bit).
.TP 3
2.
shamt : the shift amount (input, \fIY\fR bits).
.TP 3
3.
i : value to shift (input, \fIN\fR bits).
.TP 3
4.
o : output (\fIN\fR bits).
.TP 3
5.
vdd : power.
.TP 3
6.
vss : ground.
.SH "EXAMPLE"
.PP
.nf
GENLIB_MACRO(DPGEN_SHIFT, "model_shift_32",
F_BEHAV|F_PLACE,
32);
GENLIB_LOINS("model_shift_32",
"instance1_shift_32",
"op[1:0]",
"shamt[4:0]",
"x[31:0]",
"y[31:0]",
"vdd", "vss", NULL);
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)