.\" DO NOT MODIFY THIS FILE! It was generated by help2man 1.47.4.
.TH LLVM-MC "1" "February 2018" "llvm-mc 5.0" "User Commands"
.SH NAME
llvm-mc \- manual page for llvm-mc 5.0
.SH DESCRIPTION
OVERVIEW: llvm machine code playground
.PP
USAGE: llvm\-mc [options]
.PP
OPTIONS:
.PP
General options:
.HP
\fB\-I=\fR \- Directory of include files
.HP
\fB\-aarch64\-neon\-syntax\fR \- Choose style of NEON code to emit from AArch64 backend:
.TP
=generic
\- Emit generic NEON assembly
.TP
=apple
\- Emit Apple\-style NEON assembly
.HP
\fB\-amdgpu\-dump\-comd\fR \- Dump AMDGPU Code Object Metadata
.HP
\fB\-amdgpu\-enable\-merge\-m0\fR \- Merge and hoist M0 initializations
.HP
\fB\-amdgpu\-sdwa\-peephole\fR \- Enable SDWA peepholer
.HP
\fB\-amdgpu\-spill\-sgpr\-to\-smem\fR \- Use scalar stores to spill SGPRs if supported by subtarget
.HP
\fB\-amdgpu\-verify\-comd\fR \- Verify AMDGPU Code Object Metadata
.HP
\fB\-amdgpu\-vgpr\-index\-mode\fR \- Use GPR indexing mode instead of movrel for vector indexing
.HP
\fB\-arch=\fR \- Target arch to assemble for, see \fB\-version\fR for available targets
.HP
\fB\-arm\-add\-build\-attributes\fR \-
.HP
\fB\-arm\-implicit\-it\fR \- Allow conditional instructions outdside of an IT block
.TP
=always
\- Accept in both ISAs, emit implicit ITs in Thumb
.TP
=never
\- Warn in ARM, reject in Thumb
.TP
=arm
\- Accept in ARM, reject in Thumb
.TP
=thumb
\- Warn in ARM, emit implicit ITs in Thumb
.HP
\fB\-asm\-instrumentation\fR \- Instrumentation of inline assembly and assembly source files
.TP
=none
\- no instrumentation at all
.TP
=address
\- instrument instructions with memory arguments
.HP
\fB\-asm\-show\-inst\fR \- Emit internal instruction representation to assembly file
.TP
\fB\-atomic\-counter\-update\-promoted\fR \- Do counter update using atomic fetch add
for promoted counters only
.HP
\fB\-bounds\-checking\-single\-trap\fR \- Use one trap block per function
.HP
\fB\-code\-model\fR \- Choose code model
.TP
=default
\- Target default code model
.TP
=small
\- Small code model
.TP
=kernel
\- Kernel code model
.TP
=medium
\- Medium code model
.TP
=large
\- Large code model
.HP
\fB\-color\fR \- use colored syntax highlighting (default=autodetect)
.HP
\fB\-compress\-debug\-sections\fR \- Choose DWARF debug sections compression:
.TP
=none
\- No compression
.TP
=zlib
\- Use zlib compression
.TP
=zlib\-gnu
\- Use zlib\-gnu compression (deprecated)
.HP
\fB\-cvp\-dont\-process\-adds\fR \-
.HP
\fB\-debug\-counter\fR \- Comma separated list of debug counter skip and count
.TP
=predicateinfo\-rename
\- Controls which variables are renamed with predicateinfo
.TP
=newgvn\-vn
\- Controls which instructions are value numbered
.TP
=newgvn\-phi
\- Controls which instructions we create phi of ops for
.HP
\fB\-defsym=\fR \- Defines a symbol to be an integer constant
.HP
\fB\-disable\-spill\-fusing\fR \- Disable fusing of spill code into instructions
.IP
Action to perform:
.HP
\fB\-as\-lex\fR \- Lex tokens from a .s file
.HP
\fB\-assemble\fR \- Assemble a .s file (default)
.HP
\fB\-disassemble\fR \- Disassemble strings of hex bytes
.HP
\fB\-mdis\fR \- Marked up disassembly of strings of hex bytes
.HP
\fB\-do\-counter\-promotion\fR \- Do counter register promotion
.HP
\fB\-dwarf\-version=\fR \- Dwarf version
.HP
\fB\-enable\-implicit\-null\-checks\fR \- Fold null checks into faulting memory operations
.HP
\fB\-enable\-load\-pre\fR \-
.HP
\fB\-enable\-name\-compression\fR \- Enable name string compression
.HP
\fB\-enable\-objc\-arc\-opts\fR \- enable/disable all ARC Optimizations
.HP
\fB\-enable\-packed\-inlinable\-literals\fR \- Enable packed inlinable literals (v2f16, v2i16)
.HP
\fB\-enable\-scoped\-noalias\fR \-
.HP
\fB\-enable\-si\-insert\-waitcnts\fR \- Use new waitcnt insertion pass
.HP
\fB\-enable\-tbaa\fR \-
.HP
\fB\-exhaustive\-register\-search\fR \- Exhaustive Search for registers bypassing the depth and interference cutoffs of last chance recoloring
.HP
\fB\-expensive\-combines\fR \- Enable expensive instruction combines
.HP
\fB\-fatal\-warnings\fR \- Treat warnings as errors
.HP
\fB\-fdebug\-compilation\-dir=\fR \- Specifies the debug info's compilation dir
.HP
\fB\-filetype\fR \- Choose an output file type:
.TP
=asm
\- Emit an assembly ('.s') file
.TP
=null
\- Don't emit anything (for timing purposes)
.TP
=obj
\- Emit a native object ('.o') file
.HP
\fB\-filter\-print\-funcs=\fR \- Only print IR for functions whose name match this for all print\-[before|after][\-all] options
.HP
\fB\-g\fR \- Generate dwarf debugging info for assembly source files
.TP
\fB\-gpsize=\fR \- Global Pointer Addressing Size.
The default size is 8.
.HP
\fB\-hash\-based\-counter\-split\fR \- Rename counter variable of a comdat function based on cfg hash
.HP
\fB\-imp\-null\-check\-page\-size=\fR \- The page size of the target in bytes
.HP
\fB\-imp\-null\-max\-insts\-to\-consider=\fR \- The max number of instructions to consider hoisting loads over (the algorithm is quadratic over this number)
.HP
\fB\-incremental\-linker\-compatible\fR \- When used with filetype=obj, emit an object file which can be used with an incremental linker
.HP
\fB\-instcombine\-maxarray\-size=\fR \- Maximum array size considered when doing a combine
.HP
\fB\-internalize\-public\-api\-file=\fR \- A file containing list of symbol names to preserve
.HP
\fB\-internalize\-public\-api\-list=\fR \- A list of symbol names to preserve
.HP
\fB\-iterative\-counter\-promotion\fR \- Allow counter promotion across the whole loop nest.
.HP
\fB\-join\-liveintervals\fR \- Coalesce copies (default=true)
.HP
\fB\-limit\-float\-precision=\fR \- Generate low\-precision inline sequences for some float libcalls
.HP
\fB\-lto\-pass\-remarks\-output=\fR \- Output filename for pass remarks
.HP
\fB\-main\-file\-name=\fR \- Specifies the name we should consider the input file
.HP
\fB\-mattr=\fR \- Target specific attributes (\fB\-mattr\fR=\fI\,help\/\fR for details)
.HP
\fB\-max\-counter\-promotions=\fR \- Max number of allowed counter promotions
.HP
\fB\-max\-counter\-promotions\-per\-loop=\fR \- Max number counter promotions per loop to avoid increasing register pressure too much
.HP
\fB\-mc\-relax\-all\fR \- When used with filetype=obj, relax all fixups in the emitted object file
.HP
\fB\-mcpu=\fR \- Target a specific cpu type (\fB\-mcpu\fR=\fI\,help\/\fR for details)
.HP
\fB\-memop\-size\-large=\fR \- Set large value thresthold in memory intrinsic size profiling. Value of 0 disables the large value profiling.
.HP
\fB\-memop\-size\-range=\fR \- Set the range of size in memory intrinsic calls to be profiled precisely, in a format of :
.HP
\fB\-merror\-missing\-parenthesis\fR \- Error for missing parenthesis around predicate registers
.HP
\fB\-merror\-noncontigious\-register\fR \- Error for register names that aren't contigious
.HP
\fB\-mfuture\-regs\fR \- Enable future registers
.HP
\fB\-mips\-compact\-branches\fR \- MIPS Specific: Compact branch policy.
.TP
=never
\- Do not use compact branches if possible.
.TP
=optimal
\- Use compact branches where appropiate (default).
.TP
=always
\- Always use compact branches if possible.
.HP
\fB\-mips16\-constant\-islands\fR \- Enable mips16 constant islands.
.HP
\fB\-mips16\-hard\-float\fR \- Enable mips16 hard float.
.HP
\fB\-mno\-compound\fR \- Disable looking for compound instructions for Hexagon
.HP
\fB\-mno\-fixup\fR \- Disable fixing up resolved relocations for Hexagon
.HP
\fB\-mno\-ldc1\-sdc1\fR \- Expand double precision loads and stores to their single precision counterparts
.HP
\fB\-mno\-pairing\fR \- Disable looking for duplex instructions for Hexagon
.HP
\fB\-mwarn\-missing\-parenthesis\fR \- Warn for missing parenthesis around predicate registers
.HP
\fB\-mwarn\-noncontigious\-register\fR \- Warn for register names that arent contigious
.HP
\fB\-mwarn\-sign\-mismatch\fR \- Warn for mismatching a signed and unsigned value
.HP
\fB\-n\fR \- Don't assume assembly file starts in the text section
.HP
\fB\-no\-deprecated\-warn\fR \- Suppress all deprecated warnings
.HP
\fB\-no\-discriminators\fR \- Disable generation of discriminator information.
.HP
\fB\-no\-exec\-stack\fR \- File doesn't need an exec stack
.HP
\fB\-no\-warn\fR \- Suppress all warnings
.HP
\fB\-nvptx\-sched4reg\fR \- NVPTX Specific: schedule for register pressue
.HP
\fB\-o=\fR \- Output filename
.HP
\fB\-output\-asm\-variant=\fR \- Syntax variant to use for output printing
.HP
\fB\-pie\-copy\-relocations\fR \- PIE Copy Relocations
.HP
\fB\-position\-independent\fR \- Position independent
.HP
\fB\-preserve\-comments\fR \- Preserve Comments in outputted assembly
.HP
\fB\-print\-after\-all\fR \- Print IR after each pass
.HP
\fB\-print\-before\-all\fR \- Print IR before each pass
.HP
\fB\-print\-imm\-hex\fR \- Prefer hex format for immediate values
.HP
\fB\-print\-machineinstrs=\fR \- Print machine instrs
.HP
\fB\-r600\-ir\-structurize\fR \- Use StructurizeCFG IR pass
.HP
\fB\-rdf\-dump\fR \-
.HP
\fB\-rdf\-limit=\fR \-
.HP
\fB\-regalloc\fR \- Register allocator to use
.TP
=pbqp
\- PBQP register allocator
.TP
=greedy
\- greedy register allocator
.TP
=fast
\- fast register allocator
.TP
=basic
\- basic register allocator
.TP
=default
\- pick register allocator based on \fB\-O\fR option
.HP
\fB\-relax\-relocations\fR \- Emit R_X86_64_GOTPCRELX instead of R_X86_64_GOTPCREL
.HP
\fB\-rewrite\-map\-file=\fR \- Symbol Rewrite Map
.HP
\fB\-rng\-seed=\fR \- Seed for the random number generator
.HP
\fB\-safepoint\-ir\-verifier\-print\-only\fR \-
.HP
\fB\-sample\-profile\-check\-record\-coverage=\fR \- Emit a warning if less than N% of records in the input profile are matched to the IR.
.HP
\fB\-sample\-profile\-check\-sample\-coverage=\fR \- Emit a warning if less than N% of samples in the input profile are matched to the IR.
.HP
\fB\-sample\-profile\-inline\-hot\-threshold=\fR \- Inlined functions that account for more than N% of all samples collected in the parent function, will be inlined again.
.HP
\fB\-sample\-profile\-max\-propagate\-iterations=\fR \- Maximum number of iterations to go through when propagating sample block/edge weights through the CFG.
.HP
\fB\-save\-temp\-labels\fR \- Don't discard temporary labels
.HP
\fB\-show\-encoding\fR \- Show instruction encodings
.HP
\fB\-show\-inst\fR \- Show internal instruction representation
.HP
\fB\-show\-inst\-operands\fR \- Show instructions operands as parsed
.HP
\fB\-simplify\-mir\fR \- Leave out unnecessary information when printing MIR
.TP
\fB\-speculative\-counter\-promotion\-max\-exiting=\fR \- The max number of exiting blocks of a loop to allow
speculative counter promotion
.TP
\fB\-speculative\-counter\-promotion\-to\-loop\fR \- When the option is false, if the target block is in a loop, the promotion will be disallowed unless the promoted counter
update can be further/iteratively promoted into an acyclic region.
.HP
\fB\-stackmap\-version=\fR \- Specify the stackmap encoding version (default = 3)
.HP
\fB\-static\-func\-full\-module\-prefix\fR \- Use full module build paths in the profile counter names for static functions.
.HP
\fB\-static\-func\-strip\-dirname\-prefix=\fR \- Strip specified level of directory name from source path in the profile counter name for static functions.
.HP
\fB\-stats\fR \- Enable statistics output from program (available with Asserts)
.HP
\fB\-stats\-json\fR \- Display statistics as json data
.HP
\fB\-summary\-file=\fR \- The summary file to use for function importing.
.HP
\fB\-threads=\fR \-
.HP
\fB\-time\-passes\fR \- Time each pass, printing elapsed time for each on exit
.HP
\fB\-triple=\fR \- Target triple to assemble for, see \fB\-version\fR for available targets
.HP
\fB\-unfold\-element\-atomic\-memcpy\-max\-elements=\fR \- Maximum number of elements in atomic memcpy the optimizer is allowed to unfold
.HP
\fB\-verify\-debug\-info\fR \-
.HP
\fB\-verify\-dom\-info\fR \- Verify dominator info (time consuming)
.HP
\fB\-verify\-loop\-info\fR \- Verify loop info (time consuming)
.HP
\fB\-verify\-loop\-lcssa\fR \- Verify loop lcssa form (time consuming)
.HP
\fB\-verify\-machine\-dom\-info\fR \- Verify machine dominator info (time consuming)
.HP
\fB\-verify\-regalloc\fR \- Verify during register allocation
.HP
\fB\-verify\-region\-info\fR \- Verify region info (time consuming)
.HP
\fB\-verify\-scev\fR \- Verify ScalarEvolution's backedge taken counts (slow)
.HP
\fB\-verify\-scev\-maps\fR \- Verify no dangling value in ScalarEvolution's ExprValueMap (slow)
.HP
\fB\-vp\-counters\-per\-site=\fR \- The average number of profile counters allocated per value profiling site.
.HP
\fB\-vp\-static\-alloc\fR \- Do static counter allocation for value profiler
.HP
\fB\-x86\-asm\-syntax\fR \- Choose style of code to emit from X86 backend:
.TP
=att
\- Emit AT&T\-style assembly
.TP
=intel
\- Emit Intel\-style assembly
.PP
Generic Options:
.HP
\fB\-help\fR \- Display available options (\fB\-help\-hidden\fR for more)
.HP
\fB\-help\-list\fR \- Display list of available options (\fB\-help\-list\-hidden\fR for more)
.HP
\fB\-version\fR \- Display the version of this program
.SH "SEE ALSO"
The full documentation for
.B llvm-mc
is maintained as a Texinfo manual. If the
.B info
and
.B llvm-mc
programs are properly installed at your site, the command
.IP
.B info llvm-mc
.PP
should give you access to the complete manual.