.\" DO NOT MODIFY THIS FILE!  It was generated by help2man 1.46.3.
.TH LLVM-OBJDUMP "1" "October 2014" "llvm-objdump 3.4" "User Commands"
.SH NAME
llvm-objdump \- manual page for llvm-objdump 3.4
.SH DESCRIPTION
OVERVIEW: llvm object file dumper
.PP
USAGE: llvm\-objdump [options] <input object files>
.SS "OPTIONS:"
.HP
\fB\-arch=\fR<string>                          \- Target arch to disassemble for, see \fB\-version\fR for available targets
.HP
\fB\-asm\-verbose\fR                            \- Add comments to directives.
.HP
\fB\-bounds\-checking\-single\-trap\fR            \- Use one trap block per function
.HP
\fB\-cfg\fR                                    \- Create a CFG for every function found in the object and write it to a graphviz file
.HP
\fB\-cppfname=\fR<function name>               \- Specify the name of the generated function
.HP
\fB\-cppfor=\fR<string>                        \- Specify the name of the thing to generate
.HP
\fB\-cppgen\fR                                 \- Choose what kind of output to generate
.TP
=program
\-   Generate a complete program
.TP
=module
\-   Generate a module definition
.TP
=contents
\-   Generate contents of a module
.TP
=function
\-   Generate a function definition
.TP
=functions
\-   Generate all function definitions
.TP
=inline
\-   Generate an inline function
.TP
=variable
\-   Generate a variable definition
.TP
=type
\-   Generate a type definition
.HP
\fB\-disable\-debug\-info\-verifier\fR            \-
.HP
\fB\-disable\-spill\-fusing\fR                   \- Disable fusing of spill code into instructions
.HP
\fB\-disassemble\fR                            \- Display assembler mnemonics for the machine instructions
.HP
\fB\-dsym=\fR<string>                          \- Use .dSYM file for debug info
.HP
\fB\-enable\-correct\-eh\-support\fR              \- Make the \fB\-lowerinvoke\fR pass insert expensive, but correct, EH code
.HP
\fB\-enable\-load\-pre\fR                        \-
.HP
\fB\-enable\-objc\-arc\-opts\fR                   \- enable/disable all ARC Optimizations
.HP
\fB\-enable\-tbaa\fR                            \-
.HP
\fB\-fatal\-assembler\-warnings\fR               \- Consider warnings as error
.HP
\fB\-fdata\-sections\fR                         \- Emit data into separate sections
.HP
\fB\-ffunction\-sections\fR                     \- Emit functions into separate sections
.HP
\fB\-g\fR                                      \- Print line information from debug info if available
.HP
\fB\-help\fR                                   \- Display available options (\fB\-help\-hidden\fR for more)
.HP
\fB\-internalize\-public\-api\-file=\fR<filename> \- A file containing list of symbol names to preserve
.HP
\fB\-internalize\-public\-api\-list=\fR<list>     \- A list of symbol names to preserve
.HP
\fB\-join\-liveintervals\fR                     \- Coalesce copies (default=true)
.HP
\fB\-limit\-float\-precision=\fR<uint>           \- Generate low\-precision inline sequences for some float libcalls
.HP
\fB\-macho\fR                                  \- Use MachO specific object file parser
.HP
\fB\-mattr=\fR<a1,+a2,\-a3,...>                 \- Target specific attributes
.HP
\fB\-mc\-x86\-disable\-arith\-relaxation\fR        \- Disable relaxation of arithmetic instruction for X86
.HP
\fB\-mips16\-hard\-float\fR                      \- MIPS: mips16 hard float enable.
.HP
\fB\-mno\-ldc1\-sdc1\fR                          \- Expand double precision loads and stores to their single precision counterparts
.HP
\fB\-no\-show\-raw\-insn\fR                       \- When disassembling instructions, do not print the instruction bytes.
.HP
\fB\-nvptx\-sched4reg\fR                        \- NVPTX Specific: schedule for register pressue
.HP
\fB\-pre\-RA\-sched\fR                           \- Instruction schedulers available (before register allocation):
.TP
=vliw\-td
\-   VLIW scheduler
.TP
=list\-ilp
\-   Bottom\-up register pressure aware list scheduling which tries to balance ILP and register pressure
.TP
=list\-hybrid
\-   Bottom\-up register pressure aware list scheduling which tries to balance latency and register pressure
.TP
=source
\-   Similar to list\-burr but schedules in source order when possible
.TP
=list\-burr
\-   Bottom\-up register reduction list scheduling
.TP
=linearize
\-   Linearize DAG, no scheduling
.TP
=fast
\-   Fast suboptimal list scheduling
.TP
=default
\-   Best scheduler for the target
.HP
\fB\-print\-after\-all\fR                        \- Print IR after each pass
.HP
\fB\-print\-before\-all\fR                       \- Print IR before each pass
.HP
\fB\-print\-machineinstrs=\fR<pass\-name>        \- Print machine instrs
.HP
\fB\-private\-headers\fR                        \- Display format specific file headers
.HP
\fB\-r\fR                                      \- Display the relocation entries in the file
.HP
\fB\-regalloc\fR                               \- Register allocator to use
.TP
=default
\-   pick register allocator based on \fB\-O\fR option
.TP
=basic
\-   basic register allocator
.TP
=fast
\-   fast register allocator
.TP
=greedy
\-   greedy register allocator
.TP
=pbqp
\-   PBQP register allocator
.HP
\fB\-s\fR                                      \- Display the content of each section
.HP
\fB\-section\-headers\fR                        \- Display summaries of the headers for each section.
.HP
\fB\-spiller\fR                                \- Spiller to use: (default: standard)
.TP
=trivial
\-   trivial spiller
.TP
=inline
\-   inline spiller
.HP
\fB\-stats\fR                                  \- Enable statistics output from program (available with Asserts)
.HP
\fB\-symbolize\fR                              \- When disassembling instructions, try to symbolize operands.
.HP
\fB\-t\fR                                      \- Display the symbol table
.HP
\fB\-time\-passes\fR                            \- Time each pass, printing elapsed time for each on exit
.HP
\fB\-triple=\fR<string>                        \- Target triple to disassemble for, see \fB\-version\fR for available targets
.HP
\fB\-unwind\-info\fR                            \- Display unwind information
.HP
\fB\-verify\-dom\-info\fR                        \- Verify dominator info (time consuming)
.HP
\fB\-verify\-loop\-info\fR                       \- Verify loop info (time consuming)
.HP
\fB\-verify\-regalloc\fR                        \- Verify during register allocation
.HP
\fB\-verify\-region\-info\fR                     \- Verify region info (time consuming)
.HP
\fB\-verify\-scev\fR                            \- Verify ScalarEvolution's backedge taken counts (slow)
.HP
\fB\-version\fR                                \- Display the version of this program
.HP
\fB\-x86\-asm\-syntax\fR                         \- Choose style of code to emit from X86 backend:
.TP
=att
\-   Emit AT&T\-style assembly
.TP
=intel
\-   Emit Intel\-style assembly
.HP
\fB\-yaml\-cfg=\fR<yaml output file>            \- Create a CFG and write it as a YAML MCModule.
.SH "SEE ALSO"
The full documentation for
.B llvm-objdump
is maintained as a Texinfo manual.  If the
.B info
and
.B llvm-objdump
programs are properly installed at your site, the command
.IP
.B info llvm-objdump
.PP
should give you access to the complete manual.