.\" DO NOT MODIFY THIS FILE! It was generated by help2man 1.46.3.
.TH LLVM-MC "1" "October 2014" "llvm-mc 3.4" "User Commands"
.SH NAME
llvm-mc \- manual page for llvm-mc 3.4
.SH DESCRIPTION
OVERVIEW: llvm machine code playground
.PP
USAGE: llvm\-mc [options]
.SS "OPTIONS:"
.HP
\fB\-I=\fR \- Directory of include files
.HP
\fB\-L\fR \- Don't discard temporary labels
.HP
\fB\-arch=\fR \- Target arch to assemble for, see \fB\-version\fR for available targets
.HP
\fB\-asm\-verbose\fR \- Add comments to directives.
.HP
\fB\-bounds\-checking\-single\-trap\fR \- Use one trap block per function
.HP
\fB\-code\-model\fR \- Choose code model
.TP
=default
\- Target default code model
.TP
=small
\- Small code model
.TP
=kernel
\- Kernel code model
.TP
=medium
\- Medium code model
.TP
=large
\- Large code model
.HP
\fB\-cppfname=\fR \- Specify the name of the generated function
.HP
\fB\-cppfor=\fR \- Specify the name of the thing to generate
.HP
\fB\-cppgen\fR \- Choose what kind of output to generate
.TP
=program
\- Generate a complete program
.TP
=module
\- Generate a module definition
.TP
=contents
\- Generate contents of a module
.TP
=function
\- Generate a function definition
.TP
=functions
\- Generate all function definitions
.TP
=inline
\- Generate an inline function
.TP
=variable
\- Generate a variable definition
.TP
=type
\- Generate a type definition
.HP
\fB\-disable\-cfi\fR \- Do not use .cfi_* directives
.HP
\fB\-disable\-debug\-info\-verifier\fR \-
.HP
\fB\-disable\-spill\-fusing\fR \- Disable fusing of spill code into instructions
.HP
\fB\-enable\-correct\-eh\-support\fR \- Make the \fB\-lowerinvoke\fR pass insert expensive, but correct, EH code
.HP
\fB\-enable\-load\-pre\fR \-
.HP
\fB\-enable\-objc\-arc\-opts\fR \- enable/disable all ARC Optimizations
.HP
\fB\-enable\-tbaa\fR \-
.HP
\fB\-fatal\-assembler\-warnings\fR \- Consider warnings as error
.HP
\fB\-fdata\-sections\fR \- Emit data into separate sections
.HP
\fB\-fdebug\-compilation\-dir=\fR \- Specifies the debug info's compilation dir
.HP
\fB\-ffunction\-sections\fR \- Emit functions into separate sections
.HP
\fB\-filetype\fR \- Choose an output file type:
.TP
=asm
\- Emit an assembly ('.s') file
.TP
=null
\- Don't emit anything (for timing purposes)
.TP
=obj
\- Emit a native object ('.o') file
.HP
\fB\-g\fR \- Generate dwarf debugging info for assembly source files
.HP
\fB\-help\fR \- Display available options (\fB\-help\-hidden\fR for more)
.HP
\fB\-internalize\-public\-api\-file=\fR \- A file containing list of symbol names to preserve
.HP
\fB\-internalize\-public\-api\-list=\fR \- A list of symbol names to preserve
.HP
\fB\-join\-liveintervals\fR \- Coalesce copies (default=true)
.HP
\fB\-limit\-float\-precision=\fR \- Generate low\-precision inline sequences for some float libcalls
.HP
\fB\-main\-file\-name=\fR \- Specifies the name we should consider the input file
.HP
\fB\-mattr=\fR \- Target specific attributes (\fB\-mattr\fR=\fI\,help\/\fR for details)
.HP
\fB\-mc\-no\-exec\-stack\fR \- File doesn't need an exec stack
.HP
\fB\-mc\-relax\-all\fR \- Relax all fixups
.HP
\fB\-mc\-x86\-disable\-arith\-relaxation\fR \- Disable relaxation of arithmetic instruction for X86
.HP
\fB\-mcpu=\fR \- Target a specific cpu type (\fB\-mcpu\fR=\fI\,help\/\fR for details)
.IP
Action to perform:
.HP
\fB\-as\-lex\fR \- Lex tokens from a .s file
.HP
\fB\-assemble\fR \- Assemble a .s file (default)
.HP
\fB\-disassemble\fR \- Disassemble strings of hex bytes
.HP
\fB\-mdis\fR \- Marked up disassembly of strings of hex bytes
.HP
\fB\-hdis\fR \- Disassemble strings of hex bytes printing immediates as hex
.HP
\fB\-mips16\-hard\-float\fR \- MIPS: mips16 hard float enable.
.HP
\fB\-mno\-ldc1\-sdc1\fR \- Expand double precision loads and stores to their single precision counterparts
.HP
\fB\-n\fR \- Don't assume assembly file starts in the text section
.HP
\fB\-nvptx\-sched4reg\fR \- NVPTX Specific: schedule for register pressue
.HP
\fB\-o=\fR \- Output filename
.HP
\fB\-output\-asm\-variant=\fR \- Syntax variant to use for output printing
.HP
\fB\-pre\-RA\-sched\fR \- Instruction schedulers available (before register allocation):
.TP
=vliw\-td
\- VLIW scheduler
.TP
=list\-ilp
\- Bottom\-up register pressure aware list scheduling which tries to balance ILP and register pressure
.TP
=list\-hybrid
\- Bottom\-up register pressure aware list scheduling which tries to balance latency and register pressure
.TP
=source
\- Similar to list\-burr but schedules in source order when possible
.TP
=list\-burr
\- Bottom\-up register reduction list scheduling
.TP
=linearize
\- Linearize DAG, no scheduling
.TP
=fast
\- Fast suboptimal list scheduling
.TP
=default
\- Best scheduler for the target
.HP
\fB\-print\-after\-all\fR \- Print IR after each pass
.HP
\fB\-print\-before\-all\fR \- Print IR before each pass
.HP
\fB\-print\-machineinstrs=\fR \- Print machine instrs
.HP
\fB\-regalloc\fR \- Register allocator to use
.TP
=default
\- pick register allocator based on \fB\-O\fR option
.TP
=basic
\- basic register allocator
.TP
=fast
\- fast register allocator
.TP
=greedy
\- greedy register allocator
.TP
=pbqp
\- PBQP register allocator
.HP
\fB\-relocation\-model\fR \- Choose relocation model
.TP
=default
\- Target default relocation model
.TP
=static
\- Non\-relocatable code
.TP
=pic
\- Fully relocatable, position independent code
.TP
=dynamic\-no\-pic
\- Relocatable external references, non\-relocatable code
.HP
\fB\-show\-encoding\fR \- Show instruction encodings
.HP
\fB\-show\-inst\fR \- Show internal instruction representation
.HP
\fB\-show\-inst\-operands\fR \- Show instructions operands as parsed
.HP
\fB\-spiller\fR \- Spiller to use: (default: standard)
.TP
=trivial
\- trivial spiller
.TP
=inline
\- inline spiller
.HP
\fB\-stats\fR \- Enable statistics output from program (available with Asserts)
.HP
\fB\-time\-passes\fR \- Time each pass, printing elapsed time for each on exit
.HP
\fB\-triple=\fR \- Target triple to assemble for, see \fB\-version\fR for available targets
.HP
\fB\-verify\-dom\-info\fR \- Verify dominator info (time consuming)
.HP
\fB\-verify\-loop\-info\fR \- Verify loop info (time consuming)
.HP
\fB\-verify\-regalloc\fR \- Verify during register allocation
.HP
\fB\-verify\-region\-info\fR \- Verify region info (time consuming)
.HP
\fB\-verify\-scev\fR \- Verify ScalarEvolution's backedge taken counts (slow)
.HP
\fB\-version\fR \- Display the version of this program
.HP
\fB\-x86\-asm\-syntax\fR \- Choose style of code to emit from X86 backend:
.TP
=att
\- Emit AT&T\-style assembly
.TP
=intel
\- Emit Intel\-style assembly
.SH "SEE ALSO"
The full documentation for
.B llvm-mc
is maintained as a Texinfo manual. If the
.B info
and
.B llvm-mc
programs are properly installed at your site, the command
.IP
.B info llvm-mc
.PP
should give you access to the complete manual.