'\" t
.\"     Title: mtrr_add
.\"    Author: [FIXME: author] [see http://docbook.sf.net/el/author]
.\" Generator: DocBook XSL Stylesheets v1.78.1 <http://docbook.sf.net/>
.\"      Date: May 2018
.\"    Manual: Hardware Interfaces
.\"    Source: Kernel Hackers Manual 3.16.56
.\"  Language: English
.\"
.TH "MTRR_ADD" "9" "May 2018" "Kernel Hackers Manual 3\&.16\&" "Hardware Interfaces"
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.SH "NAME"
mtrr_add \- Add a memory type region
.SH "SYNOPSIS"
.HP \w'int\ mtrr_add('u
.BI "int mtrr_add(unsigned\ long\ " "base" ", unsigned\ long\ " "size" ", unsigned\ int\ " "type" ", bool\ " "increment" ");"
.SH "ARGUMENTS"
.PP
\fIbase\fR
.RS 4
Physical base address of region
.RE
.PP
\fIsize\fR
.RS 4
Physical size of region
.RE
.PP
\fItype\fR
.RS 4
Type of MTRR desired
.RE
.PP
\fIincrement\fR
.RS 4
If this is true do usage counting on the region
.RE
.SH "DESCRIPTION"
.PP
Memory type region registers control the caching on newer Intel and non Intel processors\&. This function allows drivers to request an MTRR is added\&. The details and hardware specifics of each processor\*(Aqs implementation are hidden from the caller, but nevertheless the caller should expect to need to provide a power of two size on an equivalent power of two boundary\&.
.PP
If the region cannot be added either because all regions are in use or the CPU cannot support it a negative value is returned\&. On success the register number for this entry is returned, but should be treated as a cookie only\&.
.PP
On a multiprocessor machine the changes are made to all processors\&. This is required on x86 by the Intel processors\&.
.PP
The available types are
.PP
\fBMTRR_TYPE_UNCACHABLE\fR
\- No caching
.PP
\fBMTRR_TYPE_WRBACK\fR
\- Write data back in bursts whenever
.PP
\fBMTRR_TYPE_WRCOMB\fR
\- Write data back soon but allow bursts
.PP
\fBMTRR_TYPE_WRTHROUGH\fR
\- Cache reads but not writes
.SH "BUGS"
.PP
Needs a quiet flag for the cases where drivers do not mind failures and do not wish system log messages to be sent\&.
.SH "COPYRIGHT"
.br