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.\" therefore won't be available.  \*(C` and \*(C' expand to `' in nroff,
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.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
.ie n \{\
.    ds -- \(*W-
.    ds PI pi
.    if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
.    if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\"  diablo 12 pitch
.    ds L" ""
.    ds R" ""
.    ds C` ""
.    ds C' ""
'br\}
.el\{\
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.\}
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.if n \{\
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.\}
.if t \{\
.    ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
.    ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
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.\}
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.\" ========================================================================
.\"
.IX Title "Netlist::Module 3pm"
.TH Netlist::Module 3pm "2014-09-21" "perl v5.20.1" "User Contributed Perl Documentation"
.\" For nroff, turn off justification.  Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
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.nh
.SH "NAME"
Verilog::Netlist::Module \- Module within a Verilog Netlist
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
.Vb 1
\&  use Verilog::Netlist;
\&
\&  ...
\&  my $module = $netlist\->find_module(\*(Aqmodname\*(Aq);
\&  my $cell = $self\->find_cell(\*(Aqname\*(Aq)
\&  my $port =  $self\->find_port(\*(Aqname\*(Aq)
\&  my $net =  $self\->find_net(\*(Aqname\*(Aq)
.Ve
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
A Verilog::Netlist::Module object is created by Verilog::Netlist for every
module, macromodule, primitive or program in the design.
.SH "ACCESSORS"
.IX Header "ACCESSORS"
See also Verilog::Netlist::Subclass for additional accessors and methods.
.ie n .IP "$self\->cells" 4
.el .IP "\f(CW$self\fR\->cells" 4
.IX Item "$self->cells"
Returns list of references to Verilog::Netlist::Cell in the module.
.ie n .IP "$self\->cells_sorted" 4
.el .IP "\f(CW$self\fR\->cells_sorted" 4
.IX Item "$self->cells_sorted"
Returns list of name sorted references to Verilog::Netlist::Cell in the module.
.ie n .IP "$self\->comment" 4
.el .IP "\f(CW$self\fR\->comment" 4
.IX Item "$self->comment"
Returns any comments following the definition.  keep_comments=>1 must be
passed to Verilog::Netlist::new for comments to be retained.
.ie n .IP "$self\->find_port_by_index" 4
.el .IP "\f(CW$self\fR\->find_port_by_index" 4
.IX Item "$self->find_port_by_index"
Returns the port name associated with the given index.  Indexes start at 1
(pin numbers are traditionally counted from pin 1..pin N, not starting at
zero.  This was probably an unfortunate choice, sorry.)
.ie n .IP "$self\->is_top" 4
.el .IP "\f(CW$self\fR\->is_top" 4
.IX Item "$self->is_top"
Returns true if the module has no cells referencing it (is at the top of the hierarchy.)
.ie n .IP "$self\->keyword" 4
.el .IP "\f(CW$self\fR\->keyword" 4
.IX Item "$self->keyword"
Returns the keyword used to declare the module (\*(L"module\*(R", \*(L"macromodule\*(R",
\&\*(L"primitive\*(R" or \*(L"program\*(R".)  It might at first not seem obvious that
programs are considered modules, but in most cases they contain the same
type of objects so can be handled identically.
.ie n .IP "$self\->name" 4
.el .IP "\f(CW$self\fR\->name" 4
.IX Item "$self->name"
The name of the module.
.ie n .IP "$self\->netlist" 4
.el .IP "\f(CW$self\fR\->netlist" 4
.IX Item "$self->netlist"
Reference to the Verilog::Netlist the module is under.
.ie n .IP "$self\->nets" 4
.el .IP "\f(CW$self\fR\->nets" 4
.IX Item "$self->nets"
Returns list of references to Verilog::Netlist::Net in the module.
.ie n .IP "$self\->nets_sorted" 4
.el .IP "\f(CW$self\fR\->nets_sorted" 4
.IX Item "$self->nets_sorted"
Returns list of name sorted references to Verilog::Netlist::Net in the module.
.ie n .IP "$self\->nets_and_ports_sorted" 4
.el .IP "\f(CW$self\fR\->nets_and_ports_sorted" 4
.IX Item "$self->nets_and_ports_sorted"
Returns list of name sorted references to Verilog::Netlist::Net and
Verilog::Netlist::Port in the module.
.ie n .IP "$self\->ports" 4
.el .IP "\f(CW$self\fR\->ports" 4
.IX Item "$self->ports"
Returns list of references to Verilog::Netlist::Port in the module.
.ie n .IP "$self\->ports_ordered" 4
.el .IP "\f(CW$self\fR\->ports_ordered" 4
.IX Item "$self->ports_ordered"
Returns list of references to Verilog::Netlist::Port in the module sorted
by pin number.
.ie n .IP "$self\->ports_sorted" 4
.el .IP "\f(CW$self\fR\->ports_sorted" 4
.IX Item "$self->ports_sorted"
Returns list of references to Verilog::Netlist::Port in the module sorted
by name.
.ie n .IP "$self\->statements" 4
.el .IP "\f(CW$self\fR\->statements" 4
.IX Item "$self->statements"
Returns list of references to Verilog::Netlist::ContAssign in the module.
Other statement types (Always, etc) may also be added to this list in the
future.
.ie n .IP "$self\->statements_sorted" 4
.el .IP "\f(CW$self\fR\->statements_sorted" 4
.IX Item "$self->statements_sorted"
Returns list of name sorted references to Verilog::Netlist::ContAssign in
the module.  Other statement types (Always, etc) may also be added to this
list in the future.
.SH "MEMBER FUNCTIONS"
.IX Header "MEMBER FUNCTIONS"
See also Verilog::Netlist::Subclass for additional accessors and methods.
.ie n .IP "$self\->find_cell(\fIname\fR)" 4
.el .IP "\f(CW$self\fR\->find_cell(\fIname\fR)" 4
.IX Item "$self->find_cell(name)"
Returns Verilog::Netlist::Cell matching given name.
.ie n .IP "$self\->find_port(\fIname\fR)" 4
.el .IP "\f(CW$self\fR\->find_port(\fIname\fR)" 4
.IX Item "$self->find_port(name)"
Returns Verilog::Netlist::Port matching given name.
.ie n .IP "$self\->find_net(\fIname\fR)" 4
.el .IP "\f(CW$self\fR\->find_net(\fIname\fR)" 4
.IX Item "$self->find_net(name)"
Returns Verilog::Netlist::Net matching given name.
.ie n .IP "$self\->is_libcell" 4
.el .IP "\f(CW$self\fR\->is_libcell" 4
.IX Item "$self->is_libcell"
Returns if module declared inside a `celldefine.
.ie n .IP "$self\->level" 4
.el .IP "\f(CW$self\fR\->level" 4
.IX Item "$self->level"
Returns the reverse depth of this module with respect to other modules.
Leaf modules (modules with no cells) will be level 1.  Modules which
instantiate cells of level 1 will be level 2 modules and so forth.  See
also Netlist's modules_sorted_level.
.ie n .IP "$self\->lint" 4
.el .IP "\f(CW$self\fR\->lint" 4
.IX Item "$self->lint"
Checks the module for errors.
.ie n .IP "$self\->link" 4
.el .IP "\f(CW$self\fR\->link" 4
.IX Item "$self->link"
Creates interconnections between this module and other modules.
.ie n .IP "$self\->modulename_from_filename" 4
.el .IP "\f(CW$self\fR\->modulename_from_filename" 4
.IX Item "$self->modulename_from_filename"
Uses a rough algorithm (drop the extension) to convert a filename to the
module that is expected to be inside it.
.ie n .IP "$self\->new_cell" 4
.el .IP "\f(CW$self\fR\->new_cell" 4
.IX Item "$self->new_cell"
Creates a new Verilog::Netlist::Cell.
.ie n .IP "$self\->new_port" 4
.el .IP "\f(CW$self\fR\->new_port" 4
.IX Item "$self->new_port"
Creates a new Verilog::Netlist::Port.
.ie n .IP "$self\->new_net" 4
.el .IP "\f(CW$self\fR\->new_net" 4
.IX Item "$self->new_net"
Creates a new Verilog::Netlist::Net.
.ie n .IP "$self\->dump" 4
.el .IP "\f(CW$self\fR\->dump" 4
.IX Item "$self->dump"
Prints debugging information for this module.
.ie n .IP "$self\->verilog_text" 4
.el .IP "\f(CW$self\fR\->verilog_text" 4
.IX Item "$self->verilog_text"
Returns verilog code which represents this module.  Returned as an array
that must be joined together to form the final text string.  The netlist
must be already \->link'ed for this to work correctly.
.SH "DISTRIBUTION"
.IX Header "DISTRIBUTION"
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog \s-1EDA\s0
software tool suite.  The latest version is available from \s-1CPAN\s0 and from
<http://www.veripool.org/verilog\-perl>.
.PP
Copyright 2000\-2014 by Wilson Snyder.  This package is free software; you
can redistribute it and/or modify it under the terms of either the \s-1GNU\s0
Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
.SH "AUTHORS"
.IX Header "AUTHORS"
Wilson Snyder <wsnyder@wsnyder.org>
.SH "SEE ALSO"
.IX Header "SEE ALSO"
Verilog-Perl,
Verilog::Netlist::Subclass
Verilog::Netlist