.\"Text automatically generated by txt2man
.TH fnf 1 "31 January 2010" "" ""

.SS  NAME
\fBfnf \- translate from FNF format to other formats
\fB
.SS  SYNOPSIS
.nf
.fam C
    \fBfnf\fP [\fIoptions\fP]

.fam T
.fi
.fam T
.fi
.SS  DESCRIPTION
FNF (Free Netlist Format) is an elaborated, hierarchical, register transfer level (RTL)
netlist format used to communicate design information between frontend EDA tools.
.PP
The FNF tool translates an FNF netlist to Verilog, VHDL, C, and NuSMV.
.SS  OPTIONS
Options are processed in the order they are received.
.PP
\fB-h\fP OR \fB-help\fP
Prints this information then exits.
.PP
\fB-read_fnf\fP file
Read in an FNF netlist.
.PP
\fB-write_fnf\fP file
Write out an FNF netlist.
.PP
\fB-write_nusmv\fP file
Write out an NuSMV description.
.PP
\fB-write_verilog\fP file
Write out a Verilog netlist.
.PP
\fB-write_vhdl\fP file
Write out a VHDL netlist.
.PP
\fB-write_c\fP file
.RS
.TP
.B
Write out a C model.
Appends '.c' and '.h' to file name.
.RE
.PP
\fB-write_jhdl\fP class
.RS
.TP
.B
Write out a JHDL netlist.
Appends .java to class name.
.SS  EXAMPLES
Building an FNF netlist from Verilog using Icarus:
.PP
.nf
.fam C
      $ iverilog \-Wall \-t fnf \-o my_netlist.fnf my_verilog.v

.fam T
.fi
Use FNF to produce a Verilog and C model:
.PP
.nf
.fam C
      $ fnf \-read_fnf my_netlist.fnf \-write_verilog my_netlist.v \-write_c my_netlist

.fam T
.fi
Use FNF to produce an NuSMV model:
.PP
.nf
.fam C
      $ fnf \-read_fnf my_netlist.fnf \-write_nusmv my_netlist.smv

.fam T
.fi
Use FNF to produce another FNF netlist:
.PP
.nf
.fam C
      $ fnf \-read_fnf my_netlist.fnf \-write_fnf my_netlist2.fnf

.fam T
.fi
.SS  KNOWN LIMITATIONS
General
.RS
.IP \(bu 3
No tristate support.
.IP \(bu 3
No memory support.
.IP \(bu 3
No division or modulo operators.
.RE
.PP
Icarus Verilog FNF Code Generator
.RS
.IP \(bu 3
Assumes ports and named signals have [n:0] ordering.
.IP \(bu 3
"always" blocks are constrained to the Icarus Verilog synthesizable subset.
.IP \(bu 3
All register clocks and asynchronous resets must be senitive on the rising edge.
WARNING: No errors will be issued if a design contains "negedge".
.IP \(bu 3
All arithmetic operations must be unsigned.
WARNING: No errors will be issued if a design contains signed operations.
.IP \(bu 3
Multipliers can not be embbeded in concatenations.
.RE
.PP
Verilog and VHDL Model Writer
.RS
.IP \(bu 3
Netlist is flat.
.RE
.PP
NuSMV Model Writer
.RS
.TP
.B
- 2-value model.
No X's or Z's.
.IP \(bu 3
Inputs assumed to init to 0.
.IP \(bu 3
Registers are initialized to 0.
.SS  VERSION
0.10.6
.SS  AUTHOR
Tom Hawkins
.SS  SEE ALSO
FNF and Confluence : http://www.confluent.org/
.TP
.B
Icarus Verilog
: http://www.icarus.com/eda/verilog/
.TP
.B
NuSMV
: http://nusmv.irst.itc.it/
.SS  COPYRIGHT
Copyright (C) 2004-2005 Tom Hawkins
.RE
.PP