NAME¶
addlores - create a logical resistor
ORIGIN¶
This software belongs to the ALLIANCE CAD SYSTEM developed by the ASIM team at
LIP6 laboratory of Université Pierre et Marie CURIE, in Paris,
France.
Web :
http://asim.lip6.fr/recherche/alliance/
E-mail :
alliance-users@asim.lip6.fr
SYNOPSYS¶
#include "mlo.h"
lores_list ∗addlores(ptfig,type,resi,rcon1,rcon2,name)
lofig_list ∗ptfig ;
char type ;
double resi ;
losig_list ∗rcon1, ∗rcon2 ;
const char ∗name ;
PARAMETERS¶
- ptfig
- Pointer to the figure in which the resistor should be added
- type
- Resistor type
- resi
- Resistor value in Ohms
- rcon1
- Pointer to the signal to be connected on the resistor top plate
- rcon2
- Pointer to the signal to be connected on the resistor bottom plate
- name
- Resistor instance name
DESCRIPTION¶
addlores creates a new resistor, and adds it to the list of resistors
pointed to by
ptfig -> LORES. The new resistor is added in front of
the list, and becomes itself the list head.
The
type parameter can take one value :
- RESMIM
- for a metal resistor
The
resi argument is the resistor value in Ohms.
Two connectors are created each time a resistor is added, and the
rcon1
and
rcon2 losigs are attached to the
SIG field of the
locon of the appropriate connector. The connectors names are
rcon1
and
rcon2; their direction,
DIR, are set to
'R', and
their
TYPE INTERNAL. For details on the structures, see
locon(3) and
lores(3).
RETURN VALUE¶
addlores returns a pointer to the newly created resistor.
ERRORS¶
"∗∗∗ mbk error ∗∗∗ illegal
resistor type :
type"
The type is not a legal resistor type.
EXAMPLE¶
#include "mlo.h"
void parallel_resistors(void) /∗ netlist of two parallel resistors ∗/
{
lofig_list ∗pt = NULL ;
losig_list ∗in = NULL ;
losig_list ∗out = NULL ;
pt = addlofig("parallel_resistors") ;
addlocon(pt,"in",in = givelosig(pt,0),IN) ;
addlocon(pt,"out",out = givelosig(pt,1),OUT) ;
addlores(pt,RESMIM,0.2e-6,in,out,"res1") ;
addlores(pt,RESMIM,0.2e-6,in,out,"res2") ;
}
SEE ALSO¶
mbk(1),
lofig(3),
lores(3),
locon(3),
dellores(3).
BUG REPORT¶
This tool is under development at the
ASIM department of the
LIP6
laboratory.
We need your feedback to improve documentation and tools.