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PERF_4.7-LIST(1) | perf Manual | PERF_4.7-LIST(1) |
NAME¶
perf-list - List all symbolic event typesSYNOPSIS¶
perf list [hw|sw|cache|tracepoint|pmu|event_glob]
DESCRIPTION¶
This command displays the symbolic event types which can be selected in the various perf commands with the -e option.EVENT MODIFIERS¶
Events can optionally have a modifier by appending a colon and one or more modifiers. Modifiers allow the user to restrict the events to be counted. The following modifiers exist:u - user-space counting k - kernel counting h - hypervisor counting I - non idle counting G - guest counting (in KVM guests) H - host counting (not in KVM guests) p - precise level P - use maximum detected precise level S - read sample value (PERF_SAMPLE_READ) D - pin the event to the PMU
0 - SAMPLE_IP can have arbitrary skid 1 - SAMPLE_IP must have constant skid 2 - SAMPLE_IP requested to have 0 skid 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid sample shadowing effects.
perf record -a -e cpu-cycles:p ... # use ibs op counting cycles perf record -a -e r076:p ... # same as -e cpu-cycles:p perf record -a -e r0C1:p ... # use ibs op counting micro-ops
RAW HARDWARE EVENT DESCRIPTOR¶
Even when an event is not available in a symbolic form within perf right now, it can be encoded in a per processor specific way. For instance For x86 CPUs NNN represents the raw register encoding with the layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide] Figure 30-1 Layout of IA32_PERFEVTSELx MSRs) or AMD’s PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). Note: Only the following bit fields can be set in x86 counter registers: event, umask, edge, inv, cmask. Esp. guest/host only and OS/user mode flags must be setup using EVENT MODIFIERS. Example: If the Intel docs for a QM720 Core i7 describe an event as:Event Umask Event Mask Num. Value Mnemonic Description Comment
A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and delivered by loop stream detector invert to count cycles
perf stat -e r1a8 -a sleep 1 perf record -e r1a8 ...
ARBITRARY PMUS¶
perf also supports an extended syntax for specifying raw parameters to PMUs. Using this typically requires looking up the specific event in the CPU vendor specific documentation. The available PMUs and their raw parameters can be listed withls /sys/devices/*/format
perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=1/ ...
PER SOCKET PMUS¶
Some PMUs are not associated with a core, but with a whole CPU socket. Events on these PMUs generally cannot be sampled, but only counted globally with perf stat -a. They can be bound to one logical CPU, but will measure all the CPUs in the same socket. This example measures memory bandwidth every second on the first memory controller on socket 0 of a Intel Xeon systemperf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
perf stat -I 1000 -e power/energy-cores/ -a
ACCESS RESTRICTIONS¶
For non root users generally only context switched PMU events are available. This is normally only the events in the cpu PMU, the predefined events like cycles and instructions and some software events. Other PMUs and global measurements are normally root only. Some event qualifiers, such as "any", are also root only. This can be overriden by setting the kernel.perf_event_paranoid sysctl to -1, which allows non root to use these events. For accessing trace point events perf needs to have read access to /sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed setting.TRACING¶
Some PMUs control advanced hardware tracing capabilities, such as Intel PT, that allows low overhead execution tracing. These are described in a separate intel-pt.txt document.PARAMETERIZED EVENTS¶
Some pmu events listed by perf-list will be displayed with ? in them. For example:hv_gpci/dtbp_ptitc,phys_processor_idx=?/
perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
EVENT GROUPS¶
Perf supports time based multiplexing of events, when the number of events active exceeds the number of hardware performance counters. Multiplexing can cause measurement errors when the workload changes its execution profile. When metrics are computed using formulas from event counts, it is useful to ensure some events are always measured together as a group to minimize multiplexing errors. Event groups can be specified using { }.perf stat -e '{instructions,cycles}' ...
echo 0 > /proc/sys/kernel/nmi_watchdog
LEADER SAMPLING¶
perf also supports group leader sampling using the :S specifier.perf record -e '{cycles,instructions}:S' ... perf report --group
OPTIONS¶
Without options all known events will be listed. To limit the list use: 1.hw or hardware to list hardware events
such as cache-misses, etc.
2.sw or software to list software events
such as context switches, etc.
3.cache or hwcache to list hardware cache
events such as L1-dcache-loads, etc.
4.tracepoint to list all tracepoint events,
alternatively use subsys_glob:event_glob to filter by tracepoint
subsystems such as sched, block, etc.
5.pmu to print the kernel supplied PMU
events.
6.If none of the above is matched, it will apply the
supplied glob to all events, printing the ones that match.
7.As a last resort, it will do a substring search in all
event names.
One or more types can be used at the same time, listing the events for the types
specified.
Support raw format:
1.--raw-dump, shows the raw-dump of all the
events.
2.--raw-dump
[hw|sw|cache|tracepoint|pmu|event_glob], shows the raw-dump of a certain
kind of events.
SEE ALSO¶
perf_4.7-stat(1), perf_4.7-top(1), perf_4.7-record(1), Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide[1], AMD64 Architecture Programmer’s Manual Volume 2: System Programming[2]NOTES¶
- 1.
- Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide
- 2.
- AMD64 Architecture Programmer’s Manual Volume 2: System Programming
2016-10-19 | perf |