.\" DO NOT MODIFY THIS FILE!  It was generated by help2man 1.47.4.
.TH LLVM-RTDYLD "1" "June 2017" "llvm-rtdyld 3.9" "User Commands"
.SH NAME
llvm-rtdyld \- manual page for llvm-rtdyld 3.9
.SH DESCRIPTION
ERROR: ld.so: object 'libfakeroot\-sysv.so' from LD_PRELOAD cannot be preloaded (cannot open shared object file): ignored.
OVERVIEW: llvm MC\-JIT tool
.PP
USAGE: llvm\-rtdyld [subcommand] [options] <input file>
.PP
OPTIONS:
.PP
General options:
.HP
\fB\-aarch64\-neon\-syntax\fR                            \- Choose style of NEON code to emit from AArch64 backend:
.TP
=generic
\-   Emit generic NEON assembly
.TP
=apple
\-   Emit Apple\-style NEON assembly
.HP
\fB\-amdgpu\-fast\-fdiv\fR                               \- Enable faster 2.5 ulp fdiv
.HP
\fB\-bounds\-checking\-single\-trap\fR                    \- Use one trap block per function
.HP
\fB\-check=\fR<string>                                 \- File containing RuntimeDyld verifier checks.
.HP
\fB\-color\fR                                          \- use colored syntax highlighting (default=autodetect)
.HP
\fB\-disable\-spill\-fusing\fR                           \- Disable fusing of spill code into instructions
.HP
\fB\-dylib=\fR<string>                                 \- Add library.
.HP
\fB\-enable\-implicit\-null\-checks\fR                    \- Fold null checks into faulting memory operations
.HP
\fB\-enable\-load\-pre\fR                                \-
.HP
\fB\-enable\-name\-compression\fR                        \- Enable name string compression
.HP
\fB\-enable\-objc\-arc\-opts\fR                           \- enable/disable all ARC Optimizations
.HP
\fB\-enable\-scoped\-noalias\fR                          \-
.HP
\fB\-enable\-tbaa\fR                                    \-
.HP
\fB\-entry=\fR<string>                                 \- Function to call as entry point.
.IP
Action to perform:
.HP
\fB\-execute\fR                                      \- Load, link, and execute the inputs.
.HP
\fB\-printline\fR                                    \- Load, link, and print line information for each function.
.HP
\fB\-printdebugline\fR                               \- Load, link, and print line information for each function using the debug object
.HP
\fB\-printobjline\fR                                 \- Like \fB\-printlineinfo\fR but does not load the object first
.HP
\fB\-verify\fR                                       \- Load, link and verify the resulting memory image.
.HP
\fB\-exhaustive\-register\-search\fR                     \- Exhaustive Search for registers bypassing the depth and interference cutoffs of last chance recoloring
.HP
\fB\-expensive\-combines\fR                             \- Enable expensive instruction combines
.HP
\fB\-filter\-print\-funcs=\fR<function names>            \- Only print IR for functions whose name match this for all print\-[before|after][\-all] options
.TP
\fB\-gpsize=\fR<uint>                                  \- Global Pointer Addressing Size.
The default size is 8.
.HP
\fB\-imp\-null\-check\-page\-size=\fR<int>                 \- The page size of the target in bytes
.HP
\fB\-internalize\-public\-api\-file=\fR<filename>         \- A file containing list of symbol names to preserve
.HP
\fB\-internalize\-public\-api\-list=\fR<list>             \- A list of symbol names to preserve
.HP
\fB\-join\-liveintervals\fR                             \- Coalesce copies (default=true)
.HP
\fB\-limit\-float\-precision=\fR<uint>                   \- Generate low\-precision inline sequences for some float libcalls
.HP
\fB\-mcpu=\fR<cpu\-name>                                \- Target a specific cpu type (\fB\-mcpu\fR=\fI\,help\/\fR for details)
.HP
\fB\-merror\-missing\-parenthesis\fR                     \- Error for missing parenthesis around predicate registers
.HP
\fB\-merror\-noncontigious\-register\fR                  \- Error for register names that aren't contigious
.HP
\fB\-mfuture\-regs\fR                                   \- Enable future registers
.HP
\fB\-mips\-compact\-branches\fR                          \- MIPS Specific: Compact branch policy.
.TP
=never
\-   Do not use compact branches if possible.
.TP
=optimal
\-   Use compact branches where appropiate (default).
.TP
=always
\-   Always use compact branches if possible.
.HP
\fB\-mips16\-constant\-islands\fR                        \- Enable mips16 constant islands.
.HP
\fB\-mips16\-hard\-float\fR                              \- Enable mips16 hard float.
.HP
\fB\-mno\-compound\fR                                   \- Disable looking for compound instructions for Hexagon
.HP
\fB\-mno\-fixup\fR                                      \- Disable fixing up resolved relocations for Hexagon
.HP
\fB\-mno\-ldc1\-sdc1\fR                                  \- Expand double precision loads and stores to their single precision counterparts
.HP
\fB\-mno\-pairing\fR                                    \- Disable looking for duplex instructions for Hexagon
.HP
\fB\-mwarn\-missing\-parenthesis\fR                      \- Warn for missing parenthesis around predicate registers
.HP
\fB\-mwarn\-noncontigious\-register\fR                   \- Warn for register names that arent contigious
.HP
\fB\-mwarn\-sign\-mismatch\fR                            \- Warn for mismatching a signed and unsigned value
.HP
\fB\-no\-discriminators\fR                              \- Disable generation of discriminator information.
.HP
\fB\-nvptx\-sched4reg\fR                                \- NVPTX Specific: schedule for register pressue
.HP
\fB\-preallocate\fR                                    \- Allocate memory upfront rather than on\-demand
.HP
\fB\-print\-after\-all\fR                                \- Print IR after each pass
.HP
\fB\-print\-before\-all\fR                               \- Print IR before each pass
.HP
\fB\-print\-machineinstrs=\fR<pass\-name>                \- Print machine instrs
.HP
\fB\-r600\-ir\-structurize\fR                            \- Use StructurizeCFG IR pass
.HP
\fB\-rdf\-dump\fR                                       \-
.HP
\fB\-rdf\-limit=\fR<uint>                               \-
.HP
\fB\-regalloc\fR                                       \- Register allocator to use
.TP
=default
\-   pick register allocator based on \fB\-O\fR option
.TP
=pbqp
\-   PBQP register allocator
.TP
=greedy
\-   greedy register allocator
.TP
=fast
\-   fast register allocator
.TP
=basic
\-   basic register allocator
.HP
\fB\-rewrite\-map\-file=\fR<filename>                    \- Symbol Rewrite Map
.HP
\fB\-rng\-seed=\fR<seed>                                \- Seed for the random number generator
.HP
\fB\-sample\-profile\-check\-record\-coverage=\fR<N>       \- Emit a warning if less than N% of records in the input profile are matched to the IR.
.HP
\fB\-sample\-profile\-check\-sample\-coverage=\fR<N>       \- Emit a warning if less than N% of samples in the input profile are matched to the IR.
.HP
\fB\-sample\-profile\-inline\-hot\-threshold=\fR<N>        \- Inlined functions that account for more than N% of all samples collected in the parent function, will be inlined again.
.HP
\fB\-sample\-profile\-max\-propagate\-iterations=\fR<uint> \- Maximum number of iterations to go through when propagating sample block/edge weights through the CFG.
.HP
\fB\-stackmap\-version=\fR<int>                         \- Specify the stackmap encoding version (default = 1)
.HP
\fB\-static\-func\-full\-module\-prefix\fR                 \- Use full module build paths in the profile counter names for static functions.
.HP
\fB\-stats\fR                                          \- Enable statistics output from program (available with Asserts)
.HP
\fB\-stats\-json\fR                                     \- Display statistics as json data
.HP
\fB\-summary\-file=\fR<string>                          \- The summary file to use for function importing.
.HP
\fB\-threads=\fR<int>                                  \-
.HP
\fB\-time\-passes\fR                                    \- Time each pass, printing elapsed time for each on exit
.HP
\fB\-triple=\fR<string>                                \- Target triple for disassembler
.HP
\fB\-verify\-debug\-info\fR                              \-
.HP
\fB\-verify\-dom\-info\fR                                \- Verify dominator info (time consuming)
.HP
\fB\-verify\-loop\-info\fR                               \- Verify loop info (time consuming)
.HP
\fB\-verify\-machine\-dom\-info\fR                        \- Verify machine dominator info (time consuming)
.HP
\fB\-verify\-regalloc\fR                                \- Verify during register allocation
.HP
\fB\-verify\-region\-info\fR                             \- Verify region info (time consuming)
.HP
\fB\-verify\-scev\fR                                    \- Verify ScalarEvolution's backedge taken counts (slow)
.HP
\fB\-verify\-scev\-maps\fR                               \- Verify no dangling value in ScalarEvolution's ExprValueMap (slow)
.HP
\fB\-vp\-counters\-per\-site=\fR<number>                  \- The average number of profile counters allocated per value profiling site.
.HP
\fB\-vp\-static\-alloc\fR                                \- Do static counter allocation for value profiler
.HP
\fB\-x86\-asm\-syntax\fR                                 \- Choose style of code to emit from X86 backend:
.TP
=att
\-   Emit AT&T\-style assembly
.TP
=intel
\-   Emit Intel\-style assembly
.PP
Generic Options:
.HP
\fB\-help\fR                                           \- Display available options (\fB\-help\-hidden\fR for more)
.HP
\fB\-help\-list\fR                                      \- Display list of available options (\fB\-help\-list\-hidden\fR for more)
.HP
\fB\-version\fR                                        \- Display the version of this program