'\" t
.\"     Title: __irq_alloc_domain_generic_chips
.\"    Author: 
.\" Generator: DocBook XSL Stylesheets v1.79.1 <http://docbook.sf.net/>
.\"      Date: June 2017
.\"    Manual: Generic interrupt chip
.\"    Source: Kernel Hackers Manual 4.11.3
.\"  Language: English
.\"
.TH "__IRQ_ALLOC_DOMAIN_G" "9" "June 2017" "Kernel Hackers Manual 4\&.11\&" "Generic interrupt chip"
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.SH "NAME"
__irq_alloc_domain_generic_chips \- Allocate generic chips for an irq domain
.SH "SYNOPSIS"
.HP \w'int\ __irq_alloc_domain_generic_chips('u
.BI "int __irq_alloc_domain_generic_chips(struct\ irq_domain\ *\ " "d" ", int\ " "irqs_per_chip" ", int\ " "num_ct" ", const\ char\ *\ " "name" ", irq_flow_handler_t\ " "handler" ", unsigned\ int\ " "clr" ", unsigned\ int\ " "set" ", enum\ irq_gc_flags\ " "gcflags" ");"
.SH "ARGUMENTS"
.PP
\fIstruct irq_domain * d\fR
.RS 4
irq domain for which to allocate chips
.RE
.PP
\fIint irqs_per_chip\fR
.RS 4
Number of interrupts each chip handles (max 32)
.RE
.PP
\fIint num_ct\fR
.RS 4
Number of irq_chip_type instances associated with this
.RE
.PP
\fIconst char * name\fR
.RS 4
Name of the irq chip
.RE
.PP
\fIirq_flow_handler_t handler\fR
.RS 4
Default flow handler associated with these chips
.RE
.PP
\fIunsigned int clr\fR
.RS 4
IRQ_* bits to clear in the mapping function
.RE
.PP
\fIunsigned int set\fR
.RS 4
IRQ_* bits to set in the mapping function
.RE
.PP
\fIenum irq_gc_flags gcflags\fR
.RS 4
Generic chip specific setup flags
.RE
.SH "AUTHORS"
.PP
\fBThomas Gleixner\fR <\&tglx@linutronix.de\&>
.RS 4
Author.
.RE
.PP
\fBIngo Molnar\fR <\&mingo@elte.hu\&>
.RS 4
Author.
.RE
.SH "COPYRIGHT"
.br