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.\" ========================================================================
.\"
.IX Title "Netlist::Cell 3pm"
.TH Netlist::Cell 3pm "2019-09-13" "perl v5.28.1" "User Contributed Perl Documentation"
.\" For nroff, turn off justification.  Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
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.SH "NAME"
Verilog::Netlist::Cell \- Instantiated cell within a Verilog Netlist
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
.Vb 1
\&  use Verilog::Netlist;
\&
\&  ...
\&  my $cell = $module\->find_cell(\*(Aqcellname\*(Aq);
\&  print $cell\->name;
.Ve
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
A Verilog::Netlist::Cell object is created by Verilog::Netlist for every
instantiation in the current module.
.SH "ACCESSORS"
.IX Header "ACCESSORS"
See also Verilog::Netlist::Subclass for additional accessors and methods.
.ie n .IP "$self\->comment" 4
.el .IP "\f(CW$self\fR\->comment" 4
.IX Item "$self->comment"
Returns any comments following the definition.  keep_comments=>1 must be
passed to Verilog::Netlist::new for comments to be retained.
.ie n .IP "$self\->delete" 4
.el .IP "\f(CW$self\fR\->delete" 4
.IX Item "$self->delete"
Delete the cell from the module it's under.
.ie n .IP "$self\->gateprim" 4
.el .IP "\f(CW$self\fR\->gateprim" 4
.IX Item "$self->gateprim"
True if the cell is a gate primitive instantiation (buf/cmos/etc), but not
a \s-1UDP.\s0
.ie n .IP "$self\->module" 4
.el .IP "\f(CW$self\fR\->module" 4
.IX Item "$self->module"
Pointer to the module the cell is in.
.ie n .IP "$self\->name" 4
.el .IP "\f(CW$self\fR\->name" 4
.IX Item "$self->name"
The instantiation name of the cell.
.ie n .IP "$self\->netlist" 4
.el .IP "\f(CW$self\fR\->netlist" 4
.IX Item "$self->netlist"
Reference to the Verilog::Netlist the cell is under.
.ie n .IP "$self\->pins" 4
.el .IP "\f(CW$self\fR\->pins" 4
.IX Item "$self->pins"
List of Verilog::Netlist::Pin connections for the cell.
.ie n .IP "$self\->pins_sorted" 4
.el .IP "\f(CW$self\fR\->pins_sorted" 4
.IX Item "$self->pins_sorted"
List of name sorted Verilog::Netlist::Pin connections for the cell.
.ie n .IP "$self\->range" 4
.el .IP "\f(CW$self\fR\->range" 4
.IX Item "$self->range"
The range for the cell (e.g. \*(L"[1:0]\*(R") or false (i.e. undef or "") if not
ranged.
.ie n .IP "$self\->submod" 4
.el .IP "\f(CW$self\fR\->submod" 4
.IX Item "$self->submod"
Reference to the Verilog::Netlist::Module the cell instantiates.  Only
valid after the design is linked.
.ie n .IP "$self\->submodname" 4
.el .IP "\f(CW$self\fR\->submodname" 4
.IX Item "$self->submodname"
The module name the cell instantiates (under the cell).
.SH "MEMBER FUNCTIONS"
.IX Header "MEMBER FUNCTIONS"
See also Verilog::Netlist::Subclass for additional accessors and methods.
.ie n .IP "$self\->lint" 4
.el .IP "\f(CW$self\fR\->lint" 4
.IX Item "$self->lint"
Checks the cell for errors.  Normally called by Verilog::Netlist::lint.
.ie n .IP "$self\->new_pin" 4
.el .IP "\f(CW$self\fR\->new_pin" 4
.IX Item "$self->new_pin"
Creates a new Verilog::Netlist::Pin connection for this cell.
.ie n .IP "$self\->pins_sorted" 4
.el .IP "\f(CW$self\fR\->pins_sorted" 4
.IX Item "$self->pins_sorted"
Returns all Verilog::Netlist::Pin connections for this cell.
.ie n .IP "$self\->dump" 4
.el .IP "\f(CW$self\fR\->dump" 4
.IX Item "$self->dump"
Prints debugging information for this cell.
.SH "DISTRIBUTION"
.IX Header "DISTRIBUTION"
Verilog-Perl is part of the <http://www.veripool.org/> free Verilog \s-1EDA\s0
software tool suite.  The latest version is available from \s-1CPAN\s0 and from
<http://www.veripool.org/verilog\-perl>.
.PP
Copyright 2000\-2019 by Wilson Snyder.  This package is free software; you
can redistribute it and/or modify it under the terms of either the \s-1GNU\s0
Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
.SH "AUTHORS"
.IX Header "AUTHORS"
Wilson Snyder <wsnyder@wsnyder.org>
.SH "SEE ALSO"
.IX Header "SEE ALSO"
Verilog-Perl,
Verilog::Netlist::Subclass
Verilog::Netlist