'\" t
.\"     Title: cxl-enable-region
.\"    Author: [see the "AUTHOR(S)" section]
.\" Generator: Asciidoctor 2.0.18
.\"      Date: 2023-05-03
.\"    Manual: cxl Manual
.\"    Source: cxl
.\"  Language: English
.\"
.TH "CXL\-ENABLE\-REGION" "1" "2023-05-03" "cxl" "cxl Manual"
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.SH "NAME"
cxl-enable-region \- enable specified region(s).
.SH "SYNOPSIS"
.sp
.nf
\fIcxl enable\-region <region> [<options>]\fP
.fi
.br
.SH "DESCRIPTION"
.sp
A CXL region is composed of one or more slices of CXL memdevs, with configurable
interleave settings \- both the number of interleave ways, and the interleave
granularity.
.SH "EXAMPLE"
.sp
.if n .RS 4
.nf
.fam C
# cxl enable\-region all
enabled 2 regions
.fam
.fi
.if n .RE
.SH "OPTIONS"
.sp
\-b, \-\-bus=
.RS 4
Restrict the operation to the specified bus.
.RE
.sp
\-d, \-\-decoder=
.RS 4
The root decoder to limit the operation to. Only regions that are
children of the specified decoder will be acted upon.
.RE
.sp
\-\-debug
.RS 4
Turn on additional debug messages including library debug.
.RE
.SH "COPYRIGHT"
.sp
Copyright \(co 2016 \- 2022, Intel Corporation. License GPLv2: GNU GPL
version 2 \c
.URL "http://gnu.org/licenses/gpl.html" "" "."
This is free software:
you are free to change and redistribute it.  There is NO WARRANTY, to
the extent permitted by law.
.SH "SEE ALSO"
.sp
cxl\-list(1), cxl\-disable\-region(1)