'\" t
.\"     Title: cxl-enable-port
.\"    Author: [see the "AUTHOR(S)" section]
.\" Generator: Asciidoctor 2.0.18
.\"      Date: 2023-05-03
.\"    Manual: cxl Manual
.\"    Source: cxl
.\"  Language: English
.\"
.TH "CXL\-ENABLE\-PORT" "1" "2023-05-03" "cxl" "cxl Manual"
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.SH "NAME"
cxl-enable-port \- activate / hot\-add a given CXL port
.SH "SYNOPSIS"
.sp
.nf
\fIcxl enable\-port\fP <port0> [<port1>..<portN>] [<options>]
.fi
.br
.sp
A port typically autoenables at initial device discovery. However, if it
was manually disabled this command can trigger the kernel to activate it
again. This involves detecting the state of the HDM (Host Managed Device
Memory) Decoders and validating that CXL.mem is enabled for each port in
the device\(cqs hierarchy.
.SH "OPTIONS"
.sp
\-e, \-\-endpoint
.RS 4
Toggle from treating the port arguments as Switch Port identifiers to
Endpoint Port identifiers.
.RE
.sp
\-m, \-\-enable\-memdevs
.RS 4
Try to enable descendant memdevs after enabling the port. Recall that a
memdev is only enabled after all CXL ports in its device topology
ancestry are enabled.
.RE
.sp
\-\-debug
.RS 4
Turn on additional debug messages including library debug.
.RE
.SH "COPYRIGHT"
.sp
Copyright \(co 2016 \- 2022, Intel Corporation. License GPLv2: GNU GPL
version 2 \c
.URL "http://gnu.org/licenses/gpl.html" "" "."
This is free software:
you are free to change and redistribute it.  There is NO WARRANTY, to
the extent permitted by law.
.SH "SEE ALSO"
.sp
cxl\-disable\-port(1)