.\" DO NOT MODIFY THIS FILE! It was generated by help2man 1.49.3. .TH CLANG-REPL "1" "February 2024" "clang-repl 17" "User Commands" .SH NAME clang-repl \- manual page for clang-repl 17 .SH DESCRIPTION USAGE: clang\-repl [options] [code to run] .PP OPTIONS: .PP Color Options: .HP \fB\-\-color\fR \- Use colors in output (default=autodetect) .PP General options: .HP \fB\-\-Xcc=\fR \- Argument to pass to the CompilerInvocation .HP \fB\-\-aarch64\-neon\-syntax=\fR \- Choose style of NEON code to emit from AArch64 backend: .TP =generic \- Emit generic NEON assembly .TP =apple \- Emit Apple\-style NEON assembly .HP \fB\-\-aarch64\-use\-aa\fR \- Enable the use of AA during codegen. .HP \fB\-\-abort\-on\-max\-devirt\-iterations\-reached\fR \- Abort when the max iterations for devirtualization CGSCC repeat pass is reached .HP \fB\-\-allow\-ginsert\-as\-artifact\fR \- Allow G_INSERT to be considered an artifact. Hack around AMDGPU test infinite loops. .HP \fB\-\-amdgpu\-atomic\-optimizer\-strategy=\fR \- Select DPP or Iterative strategy for scan .TP =DPP \- Use DPP operations for scan .TP =Iterative \- Use Iterative approach for scan .TP =None \- Disable atomic optimizer .HP \fB\-\-amdgpu\-bypass\-slow\-div\fR \- Skip 64\-bit divide for dynamic 32\-bit values .HP \fB\-\-amdgpu\-disable\-loop\-alignment\fR \- Do not align and prefetch loops .HP \fB\-\-amdgpu\-dpp\-combine\fR \- Enable DPP combiner .HP \fB\-\-amdgpu\-dump\-hsa\-metadata\fR \- Dump AMDGPU HSA Metadata .HP \fB\-\-amdgpu\-enable\-merge\-m0\fR \- Merge and hoist M0 initializations .HP \fB\-\-amdgpu\-enable\-power\-sched\fR \- Enable scheduling to minimize mAI power bursts .HP \fB\-\-amdgpu\-promote\-alloca\-to\-vector\-limit=\fR \- Maximum byte size to consider promote alloca to vector .HP \fB\-\-amdgpu\-sdwa\-peephole\fR \- Enable SDWA peepholer .HP \fB\-\-amdgpu\-use\-aa\-in\-codegen\fR \- Enable the use of AA during codegen. .HP \fB\-\-amdgpu\-verify\-hsa\-metadata\fR \- Verify AMDGPU HSA Metadata .HP \fB\-\-amdgpu\-vgpr\-index\-mode\fR \- Use GPR indexing mode instead of movrel for vector indexing .HP \fB\-\-arm\-add\-build\-attributes\fR \- .HP \fB\-\-arm\-implicit\-it=\fR \- Allow conditional instructions outdside of an IT block .TP =always \- Accept in both ISAs, emit implicit ITs in Thumb .TP =never \- Warn in ARM, reject in Thumb .TP =arm \- Accept in ARM, reject in Thumb .TP =thumb \- Warn in ARM, emit implicit ITs in Thumb .HP \fB\-\-asm\-show\-inst\fR \- Emit internal instruction representation to assembly file .TP \fB\-\-atomic\-counter\-update\-promoted\fR \- Do counter update using atomic fetch add for promoted counters only .HP \fB\-\-atomic\-first\-counter\fR \- Use atomic fetch add for first counter in a function (usually the entry counter) .HP \fB\-\-bounds\-checking\-single\-trap\fR \- Use one trap block per function .HP \fB\-\-bpf\-stack\-size=\fR \- Specify the BPF stack size limit .HP \fB\-\-cfg\-hide\-cold\-paths=\fR \- Hide blocks with relative frequency below the given value .HP \fB\-\-cfg\-hide\-deoptimize\-paths\fR \- .HP \fB\-\-cfg\-hide\-unreachable\-paths\fR \- .HP \fB\-\-cost\-kind=\fR \- Target cost kind .TP =throughput \- Reciprocal throughput .TP =latency \- Instruction latency .TP =code\-size \- Code size .TP =size\-latency \- Code size and latency .HP \fB\-\-cs\-profile\-generate\fR \- Perform context sensitive PGO instrumentation .HP \fB\-\-cs\-profile\-path=\fR \- Context sensitive profile file path .HP \fB\-\-debug\-info\-correlate\fR \- Use debug info to correlate profiles. .HP \fB\-\-debugify\-func\-limit=\fR \- Set max number of processed functions per pass. .HP \fB\-\-debugify\-level=\fR \- Kind of debug info to add .TP =locations \- Locations only .TP =location+variables \- Locations and Variables .HP \fB\-\-debugify\-quiet\fR \- Suppress verbose debugify output .HP \fB\-\-disable\-auto\-upgrade\-debug\-info\fR \- Disable autoupgrade of debug info .HP \fB\-\-disable\-i2p\-p2i\-opt\fR \- Disables inttoptr/ptrtoint roundtrip optimization .HP \fB\-\-disable\-promote\-alloca\-to\-lds\fR \- Disable promote alloca to LDS .HP \fB\-\-disable\-promote\-alloca\-to\-vector\fR \- Disable promote alloca to vector .HP \fB\-\-do\-counter\-promotion\fR \- Do counter register promotion .HP \fB\-\-dot\-cfg\-mssa=\fR \- file name for generated dot file .HP \fB\-\-dwarf\-version=\fR \- Dwarf version .HP \fB\-\-dwarf64\fR \- Generate debugging info in the 64\-bit DWARF format .HP \fB\-\-emit\-compact\-unwind\-non\-canonical\fR \- Whether to try to emit Compact Unwind for non canonical entries. .HP \fB\-\-emit\-dwarf\-unwind=\fR \- Whether to emit DWARF EH frame entries. .TP =always \- Always emit EH frame entries .TP =no\-compact\-unwind \- Only emit EH frame entries when compact unwind is not available .TP =default \- Use target platform default .HP \fB\-\-emscripten\-cxx\-exceptions\-allowed=\fR \- The list of function names in which Emscripten\-style exception handling is enabled (see emscripten EMSCRIPTEN_CATCHING_ALLOWED options) .HP \fB\-\-enable\-cse\-in\-irtranslator\fR \- Should enable CSE in irtranslator .HP \fB\-\-enable\-cse\-in\-legalizer\fR \- Should enable CSE in Legalizer .HP \fB\-\-enable\-emscripten\-cxx\-exceptions\fR \- WebAssembly Emscripten\-style exception handling .HP \fB\-\-enable\-emscripten\-sjlj\fR \- WebAssembly Emscripten\-style setjmp/longjmp handling .HP \fB\-\-enable\-gvn\-hoist\fR \- Enable the GVN hoisting pass (default = off) .HP \fB\-\-enable\-gvn\-memdep\fR \- .HP \fB\-\-enable\-gvn\-sink\fR \- Enable the GVN sinking pass (default = off) .HP \fB\-\-enable\-load\-in\-loop\-pre\fR \- .HP \fB\-\-enable\-load\-pre\fR \- .HP \fB\-\-enable\-loop\-simplifycfg\-term\-folding\fR \- .HP \fB\-\-enable\-name\-compression\fR \- Enable name/filename string compression .HP \fB\-\-enable\-split\-backedge\-in\-load\-pre\fR \- .HP \fB\-\-execute\-concurrency=\fR \- The number of threads used to process all files in parallel. Set to 0 for hardware concurrency. This flag only applies to all\-TUs. .HP \fB\-\-executor=\fR \- The name of the executor to use. .HP \fB\-\-experimental\-debug\-variable\-locations\fR \- Use experimental new value\-tracking variable locations .HP \fB\-\-fatal\-warnings\fR \- Treat warnings as errors .HP \fB\-\-filter=\fR \- Only process files that match this filter. This flag only applies to all\-TUs. .HP \fB\-\-force\-tail\-folding\-style=\fR \- Force the tail folding style .TP =none \- Disable tail folding .TP =data \- Create lane mask for data only, using active.lane.mask intrinsic .TP =data\-without\-lane\-mask \- Create lane mask with compare/stepvector .TP =data\-and\-control \- Create lane mask using active.lane.mask intrinsic, and use it for both data and control flow .TP =data\-and\-control\-without\-rt\-check \- Similar to data\-and\-control, but remove the runtime check .TP \fB\-\-fs\-profile\-debug\-bw\-threshold=\fR \- Only show debug message if the source branch weight is greater than this value. .HP \fB\-\-fs\-profile\-debug\-prob\-diff\-threshold=\fR \- Only show debug message if the branch probility is greater than this value (in percentage). .HP \fB\-\-generate\-merged\-base\-profiles\fR \- When generating nested context\-sensitive profiles, always generate extra base profile for function with all its context profiles merged into it. .TP \fB\-\-gpsize=\fR \- Global Pointer Addressing Size. The default size is 8. .HP \fB\-\-hash\-based\-counter\-split\fR \- Rename counter variable of a comdat function based on cfg hash .HP \fB\-\-hexagon\-rdf\-limit=\fR \- .HP \fB\-\-hot\-cold\-split\fR \- Enable hot\-cold splitting pass .HP \fB\-\-import\-all\-index\fR \- Import all external functions in index. .HP \fB\-\-incremental\-linker\-compatible\fR \- When used with filetype=obj, emit an object file which can be used with an incremental linker .HP \fB\-\-instcombine\-code\-sinking\fR \- Enable code sinking .HP \fB\-\-instcombine\-guard\-widening\-window=\fR \- How wide an instruction window to bypass looking for another guard .HP \fB\-\-instcombine\-max\-num\-phis=\fR \- Maximum number phis to handle in intptr/ptrint folding .HP \fB\-\-instcombine\-max\-sink\-users=\fR \- Maximum number of undroppable users for instruction sinking .HP \fB\-\-instcombine\-maxarray\-size=\fR \- Maximum array size considered when doing a combine .HP \fB\-\-instcombine\-negator\-enabled\fR \- Should we attempt to sink negations? .HP \fB\-\-instcombine\-negator\-max\-depth=\fR \- What is the maximal lookup depth when trying to check for viability of negation sinking. .HP \fB\-\-instrprof\-atomic\-counter\-update\-all\fR \- Make all profile counter updates atomic (for testing only) .HP \fB\-\-internalize\-public\-api\-file=\fR \- A file containing list of symbol names to preserve .HP \fB\-\-internalize\-public\-api\-list=\fR \- A list of symbol names to preserve .HP \fB\-\-iterative\-counter\-promotion\fR \- Allow counter promotion across the whole loop nest. .HP \fB\-\-lto\-aix\-system\-assembler=\fR \- Path to a system assembler, picked up on AIX only .HP \fB\-\-lto\-embed\-bitcode=\fR \- Embed LLVM bitcode in object files produced by LTO .TP =none \- Do not embed .TP =optimized \- Embed after all optimization passes .TP =post\-merge\-pre\-opt \- Embed post merge, but before optimizations .HP \fB\-\-lto\-pass\-remarks\-filter=\fR \- Only record optimization remarks from passes whose names match the given regular expression .HP \fB\-\-lto\-pass\-remarks\-format=\fR \- The format used for serializing remarks (default: YAML) .HP \fB\-\-lto\-pass\-remarks\-output=\fR \- Output filename for pass remarks .HP \fB\-\-matrix\-default\-layout=\fR \- Sets the default matrix layout .TP =column\-major \- Use column\-major layout .TP =row\-major \- Use row\-major layout .HP \fB\-\-matrix\-print\-after\-transpose\-opt\fR \- .HP \fB\-\-max\-counter\-promotions=\fR \- Max number of allowed counter promotions .HP \fB\-\-max\-counter\-promotions\-per\-loop=\fR \- Max number counter promotions per loop to avoid increasing register pressure too much .HP \fB\-\-mc\-relax\-all\fR \- When used with filetype=obj, relax all fixups in the emitted object file .HP \fB\-\-mcabac\fR \- tbd .HP \fB\-\-merror\-missing\-parenthesis\fR \- Error for missing parenthesis around predicate registers .HP \fB\-\-merror\-noncontigious\-register\fR \- Error for register names that aren't contigious .HP \fB\-\-mhvx\fR \- Enable Hexagon Vector eXtensions .HP \fB\-\-mhvx=\fR \- Enable Hexagon Vector eXtensions .TP =v60 \- Build for HVX v60 .TP =v62 \- Build for HVX v62 .TP =v65 \- Build for HVX v65 .TP =v66 \- Build for HVX v66 .TP =v67 \- Build for HVX v67 .TP =v68 \- Build for HVX v68 .TP =v69 \- Build for HVX v69 .TP =v71 \- Build for HVX v71 .TP =v73 \- Build for HVX v73 .HP \fB\-\-mips\-compact\-branches=\fR \- MIPS Specific: Compact branch policy. .TP =never \- Do not use compact branches if possible. .TP =optimal \- Use compact branches where appropriate (default). .TP =always \- Always use compact branches if possible. .HP \fB\-\-mips16\-constant\-islands\fR \- Enable mips16 constant islands. .HP \fB\-\-mips16\-hard\-float\fR \- Enable mips16 hard float. .HP \fB\-\-mir\-strip\-debugify\-only\fR \- Should mir\-strip\-debug only strip debug info from debugified modules by default .HP \fB\-\-misexpect\-tolerance=\fR \- Prevents emiting diagnostics when profile counts are within N% of the threshold.. .HP \fB\-\-mno\-compound\fR \- Disable looking for compound instructions for Hexagon .HP \fB\-\-mno\-fixup\fR \- Disable fixing up resolved relocations for Hexagon .HP \fB\-\-mno\-ldc1\-sdc1\fR \- Expand double precision loads and stores to their single precision counterparts .HP \fB\-\-mno\-pairing\fR \- Disable looking for duplex instructions for Hexagon .HP \fB\-\-mwarn\-missing\-parenthesis\fR \- Warn for missing parenthesis around predicate registers .HP \fB\-\-mwarn\-noncontigious\-register\fR \- Warn for register names that arent contigious .HP \fB\-\-mwarn\-sign\-mismatch\fR \- Warn for mismatching a signed and unsigned value .HP \fB\-\-no\-deprecated\-warn\fR \- Suppress all deprecated warnings .HP \fB\-\-no\-discriminators\fR \- Disable generation of discriminator information. .HP \fB\-\-no\-type\-check\fR \- Suppress type errors (Wasm) .HP \fB\-\-no\-warn\fR \- Suppress all warnings .HP \fB\-\-nvptx\-sched4reg\fR \- NVPTX Specific: schedule for register pressue .HP \fB\-\-pgo\-block\-coverage\fR \- Use this option to enable basic block coverage instrumentation .HP \fB\-\-pgo\-temporal\-instrumentation\fR \- Use this option to enable temporal instrumentation .HP \fB\-\-pgo\-view\-block\-coverage\-graph\fR \- Create a dot file of CFGs with block coverage inference information .HP \fB\-\-poison\-checking\-function\-local\fR \- Check that returns are non\-poison (for testing) .HP \fB\-\-print\-pipeline\-passes\fR \- Print a '\-passes' compatible string describing the pipeline (best\-effort only). .HP \fB\-\-r600\-ir\-structurize\fR \- Use StructurizeCFG IR pass .HP \fB\-\-riscv\-add\-build\-attributes\fR \- .HP \fB\-\-runtime\-counter\-relocation\fR \- Enable relocating counters at runtime. .HP \fB\-\-safepoint\-ir\-verifier\-print\-only\fR \- .HP \fB\-\-sample\-profile\-check\-record\-coverage=\fR \- Emit a warning if less than N% of records in the input profile are matched to the IR. .HP \fB\-\-sample\-profile\-check\-sample\-coverage=\fR \- Emit a warning if less than N% of samples in the input profile are matched to the IR. .HP \fB\-\-sample\-profile\-max\-propagate\-iterations=\fR \- Maximum number of iterations to go through when propagating sample block/edge weights through the CFG. .HP \fB\-\-sanitizer\-early\-opt\-ep\fR \- Insert sanitizers on OptimizerEarlyEP. .HP \fB\-\-skip\-ret\-exit\-block\fR \- Suppress counter promotion if exit blocks contain ret. .TP \fB\-\-speculative\-counter\-promotion\-max\-exiting=\fR \- The max number of exiting blocks of a loop to allow speculative counter promotion .TP \fB\-\-speculative\-counter\-promotion\-to\-loop\fR \- When the option is false, if the target block is in a loop, the promotion will be disallowed unless the promoted counter update can be further/iteratively promoted into an acyclic region. .HP \fB\-\-summary\-file=\fR \- The summary file to use for function importing. .TP \fB\-\-sve\-tail\-folding=\fR \- Control the use of vectorisation using tail\-folding for SVE where the option is specified in the form (Initial)[+(Flag1|Flag2|...)]: disabled (Initial) No loop types will vectorize using tail\-folding default (Initial) Uses the default tail\-folding settings for the target CPU all (Initial) All legal loop types will vectorize using tail\-folding simple (Initial) Use tail\-folding for simple loops (not reductions or recurrences) reductions Use tail\-folding for loops containing reductions noreductions Inverse of above recurrences Use tail\-folding for loops containing fixed order recurrences norecurrences Inverse of above reverse Use tail\-folding for loops requiring reversed predicates noreverse Inverse of above .HP \fB\-\-tail\-predication=\fR \- MVE tail\-predication pass options .TP =disabled \- Don't tail\-predicate loops .TP =enabled\-no\-reductions \- Enable tail\-predication, but not for reduction loops .TP =enabled \- Enable tail\-predication, including reduction loops .TP =force\-enabled\-no\-reductions \- Enable tail\-predication, but not for reduction loops, and force this which might be unsafe .TP =force\-enabled \- Enable tail\-predication, including reduction loops, and force this which might be unsafe .HP \fB\-\-thinlto\-assume\-merged\fR \- Assume the input has already undergone ThinLTO function importing and the other pre\-optimization pipeline changes. .HP \fB\-\-threads=\fR \- .HP \fB\-\-type\-based\-intrinsic\-cost\fR \- Calculate intrinsics cost based only on argument types .HP \fB\-\-verify\-region\-info\fR \- Verify region info (time consuming) .HP \fB\-\-vp\-counters\-per\-site=\fR \- The average number of profile counters allocated per value profiling site. .HP \fB\-\-vp\-static\-alloc\fR \- Do static counter allocation for value profiler .HP \fB\-\-wasm\-enable\-eh\fR \- WebAssembly exception handling .HP \fB\-\-wasm\-enable\-sjlj\fR \- WebAssembly setjmp/longjmp handling .TP \fB\-\-x86\-align\-branch=\fR \- Specify types of branches to align (plus separated list of types): jcc indicates conditional jumps fused indicates fused conditional jumps jmp indicates direct unconditional jumps call indicates direct and indirect calls ret indicates rets indirect indicates indirect unconditional jumps .HP \fB\-\-x86\-align\-branch\-boundary=\fR \- Control how the assembler should align branches with NOP. If the boundary's size is not 0, it should be a power of 2 and no less than 32. Branches will be aligned to prevent from being across or against the boundary of specified size. The default value 0 does not align branches. .TP \fB\-\-x86\-branches\-within\-32B\-boundaries\fR \- Align selected instructions to mitigate negative performance impact of Intel's micro code update for errata skx102. May break assumptions about labels corresponding to particular instructions, and should be used with caution. .HP \fB\-\-x86\-pad\-max\-prefix\-size=\fR \- Maximum number of prefixes to use for padding .PP Generic Options: .HP \fB\-\-help\fR \- Display available options (\fB\-\-help\-hidden\fR for more) .HP \fB\-\-help\-list\fR \- Display list of available options (\fB\-\-help\-list\-hidden\fR for more) .HP \fB\-\-version\fR \- Display the version of this program .PP Polly Options: Configure the polly loop optimizer .HP \fB\-\-polly\fR \- Enable the polly optimizer (with \fB\-O1\fR, \fB\-O2\fR or \fB\-O3\fR) .HP \fB\-\-polly\-2nd\-level\-tiling\fR \- Enable a 2nd level loop of loop tiling .HP \fB\-\-polly\-ast\-print\-accesses\fR \- Print memory access functions .HP \fB\-\-polly\-context=\fR \- Provide additional constraints on the context parameters .HP \fB\-\-polly\-dce\-precise\-steps=\fR \- The number of precise steps between two approximating iterations. (A value of \fB\-1\fR schedules another approximation stage before the actual dead code elimination. .HP \fB\-\-polly\-delicm\-max\-ops=\fR \- Maximum number of isl operations to invest for lifetime analysis; 0=no limit .HP \fB\-\-polly\-detect\-full\-functions\fR \- Allow the detection of full functions .HP \fB\-\-polly\-dump\-after\fR \- Dump module after Polly transformations into a file suffixed with "\-after" .HP \fB\-\-polly\-dump\-after\-file=\fR \- Dump module after Polly transformations to the given file .HP \fB\-\-polly\-dump\-before\fR \- Dump module before Polly transformations into a file suffixed with "\-before" .HP \fB\-\-polly\-dump\-before\-file=\fR \- Dump module before Polly transformations to the given file .HP \fB\-\-polly\-enable\-simplify\fR \- Simplify SCoP after optimizations .HP \fB\-\-polly\-ignore\-func=\fR \- Ignore functions that match a regex. Multiple regexes can be comma separated. Scop detection will ignore all functions that match ANY of the regexes provided. .HP \fB\-\-polly\-isl\-arg=\fR \- Option passed to ISL .HP \fB\-\-polly\-matmul\-opt\fR \- Perform optimizations of matrix multiplications based on pattern matching .HP \fB\-\-polly\-on\-isl\-error\-abort\fR \- Abort if an isl error is encountered .HP \fB\-\-polly\-only\-func=\fR \- Only run on functions that match a regex. Multiple regexes can be comma separated. Scop detection will run on all functions that match ANY of the regexes provided. .HP \fB\-\-polly\-only\-region=\fR \- Only run on certain regions (The provided identifier must appear in the name of the region's entry block .HP \fB\-\-polly\-only\-scop\-detection\fR \- Only run scop detection, but no other optimizations .HP \fB\-\-polly\-optimized\-scops\fR \- Polly \- Dump polyhedral description of Scops optimized with the isl scheduling optimizer and the set of post\-scheduling transformations is applied on the schedule tree .HP \fB\-\-polly\-parallel\fR \- Generate thread parallel code (isl codegen only) .HP \fB\-\-polly\-parallel\-force\fR \- Force generation of thread parallel code ignoring any cost model .HP \fB\-\-polly\-pattern\-matching\-based\-opts\fR \- Perform optimizations based on pattern matching .HP \fB\-\-polly\-postopts\fR \- Apply post\-rescheduling optimizations such as tiling (requires \fB\-polly\-reschedule\fR) .HP \fB\-\-polly\-pragma\-based\-opts\fR \- Apply user\-directed transformation from metadata .HP \fB\-\-polly\-pragma\-ignore\-depcheck\fR \- Skip the dependency check for pragma\-based transformations .HP \fB\-\-polly\-process\-unprofitable\fR \- Process scops that are unlikely to benefit from Polly optimizations. .HP \fB\-\-polly\-register\-tiling\fR \- Enable register tiling .HP \fB\-\-polly\-report\fR \- Print information about the activities of Polly .HP \fB\-\-polly\-reschedule\fR \- Optimize SCoPs using ISL .HP \fB\-\-polly\-show\fR \- Highlight the code regions that will be optimized in a (CFG BBs and LLVM\-IR instructions) .HP \fB\-\-polly\-show\-only\fR \- Highlight the code regions that will be optimized in a (CFG only BBs) .HP \fB\-\-polly\-stmt\-granularity=\fR \- Algorithm to use for splitting basic blocks into multiple statements .TP =bb \- One statement per basic block .TP =scalar\-indep \- Scalar independence heuristic .TP =store \- Store\-level granularity .HP \fB\-\-polly\-tc\-opt\fR \- Perform optimizations of tensor contractions based on pattern matching .HP \fB\-\-polly\-tiling\fR \- Enable loop tiling .HP \fB\-\-polly\-vectorizer=\fR \- Select the vectorization strategy .TP =none \- No Vectorization .TP =stripmine \- Strip\-mine outer loops for the loop\-vectorizer to trigger