.\" Automatically generated by Pandoc 2.2.1
.\"
.TH "mlx5dv_devx_umem_reg, mlx5dv_devx_umem_dereg" "3" "" "" ""
.hy
.SH NAME
.PP
mlx5dv_devx_umem_reg \- Register a user memory to be used by the devx
interface
.PP
mlx5dv_devx_umem_dereg \- Deregister a devx umem object
.SH SYNOPSIS
.IP
.nf
\f[C]
#include\ <infiniband/mlx5dv.h>

struct\ mlx5dv_devx_umem\ {
\ \ \ \ uint32_t\ umem_id;
};

struct\ mlx5dv_devx_umem\ *
mlx5dv_devx_umem_reg(struct\ ibv_context\ *context,\ void\ *addr,\ size_t\ size,
\ \ \ \ \ \ \ \ \ \ \ \ \ uint32_t\ access)

int\ mlx5dv_devx_umem_dereg(struct\ mlx5dv_devx_umem\ *dv_devx_umem)
\f[]
.fi
.SH DESCRIPTION
.PP
Register or deregister a user memory to be used by the devx interface.
.PP
The register verb exposes a UMEM DEVX object for user memory
registration for DMA.
The API to register the user memory gets as input the user address,
length and access flags, and provides to the user as output an object
which holds the UMEM ID returned by the firmware to this registered
memory.
.PP
The user will use that UMEM ID in device direct commands that use this
memory instead of the physical addresses list, for example upon
\f[I]mlx5dv_devx_obj_create\f[] to create a QP.
.SH ARGUMENTS
.TP
.B \f[I]context\f[]
.IP
.nf
\f[C]
RDMA\ device\ context\ to\ create\ the\ action\ on.
\f[]
.fi
.RS
.RE
.TP
.B \f[I]addr\f[]
The memory start address to register.
.RS
.RE
.TP
.B \f[I]size\f[]
.IP
.nf
\f[C]
The\ size\ of\ *addr*\ buffer.
\f[]
.fi
.RS
.RE
.TP
.B \f[I]access\f[]
The desired memory protection attributes; it is either 0 or the bitwise
OR of one or more of \f[I]enum ibv_access_flags\f[].
.RS
.RE
.SH RETURN VALUE
.PP
Upon success \f[I]mlx5dv_devx_umem_reg\f[] will return a new \f[I]struct
mlx5dv_devx_umem\f[] object, on error NULL will be returned and errno
will be set.
.PP
\f[I]mlx5dv_devx_umem_dereg\f[] returns 0 on success, or the value of
errno on failure (which indicates the failure reason).
.SH SEE ALSO
.PP
\f[I]mlx5dv_open_device(3)\f[], \f[I]ibv_reg_mr(3)\f[],
\f[I]mlx5dv_devx_obj_create(3)\f[]
.PP
#AUTHOR
.PP
Yishai Hadas <yishaih@mellanox.com>