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.\" ========================================================================
.\"
.IX Title "Netlist::ModPort 3pm"
.TH Netlist::ModPort 3pm "2020-11-09" "perl v5.32.0" "User Contributed Perl Documentation"
.\" For nroff, turn off justification. Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
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.nh
.SH "NAME"
Verilog::Netlist::ModPort \- ModPort within a Verilog Interface
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
.Vb 1
\& use Verilog::Netlist;
\&
\& ...
\& my $interface = $netlist\->find_interface(\*(Aqname\*(Aq);
\& my $modport = $interface\->find_modport(\*(Aqname\*(Aq)
.Ve
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
A Verilog::Netlist::ModPort object is created by
Verilog::Netlist::Interface for every modport under the interface.
.SH "METHODS"
.IX Header "METHODS"
See also Verilog::Netlist::Subclass for additional accessors and methods.
.ie n .IP "$self\->comment" 4
.el .IP "\f(CW$self\fR\->comment" 4
.IX Item "$self->comment"
Returns any comments following the definition. keep_comments=>1 must be
passed to Verilog::Netlist::new for comments to be retained.
.ie n .IP "$self\->dump" 4
.el .IP "\f(CW$self\fR\->dump" 4
.IX Item "$self->dump"
Prints debugging information for this modport.
.ie n .IP "$self\->find_port(\fIname\fR)" 4
.el .IP "\f(CW$self\fR\->find_port(\fIname\fR)" 4
.IX Item "$self->find_port(name)"
Returns Verilog::Netlist::Net matching given name.
.ie n .IP "$self\->find_port_by_index" 4
.el .IP "\f(CW$self\fR\->find_port_by_index" 4
.IX Item "$self->find_port_by_index"
Returns the port name associated with the given index.
.ie n .IP "$self\->module" 4
.el .IP "\f(CW$self\fR\->module" 4
.IX Item "$self->module"
Returns Verilog::Netlist::Interface the ModPort belongs to.
.ie n .IP "$self\->lint" 4
.el .IP "\f(CW$self\fR\->lint" 4
.IX Item "$self->lint"
Checks the modport for errors.
.ie n .IP "$self\->name" 4
.el .IP "\f(CW$self\fR\->name" 4
.IX Item "$self->name"
The name of the modport.
.ie n .IP "$self\->netlist" 4
.el .IP "\f(CW$self\fR\->netlist" 4
.IX Item "$self->netlist"
Reference to the Verilog::Netlist the modport is under.
.ie n .IP "$self\->nets" 4
.el .IP "\f(CW$self\fR\->nets" 4
.IX Item "$self->nets"
Returns list of references to Verilog::Netlist::Net in the interface.
.ie n .IP "$self\->nets_sorted" 4
.el .IP "\f(CW$self\fR\->nets_sorted" 4
.IX Item "$self->nets_sorted"
Returns list of name sorted references to Verilog::Netlist::Net in the
interface.
.ie n .IP "$self\->nets_and_ports_sorted" 4
.el .IP "\f(CW$self\fR\->nets_and_ports_sorted" 4
.IX Item "$self->nets_and_ports_sorted"
Returns list of name sorted references to Verilog::Netlist::Net and
Verilog::Netlist::Port in the modport.
.ie n .IP "$self\->ports" 4
.el .IP "\f(CW$self\fR\->ports" 4
.IX Item "$self->ports"
Returns list of references to Verilog::Netlist::Port in the modport.
.ie n .IP "$self\->ports_ordered" 4
.el .IP "\f(CW$self\fR\->ports_ordered" 4
.IX Item "$self->ports_ordered"
Returns list of references to Verilog::Netlist::Port in the modport
sorted by pin number.
.ie n .IP "$self\->ports_sorted" 4
.el .IP "\f(CW$self\fR\->ports_sorted" 4
.IX Item "$self->ports_sorted"
Returns list of references to Verilog::Netlist::Port in the modport
sorted by name.
.ie n .IP "$self\->verilog_text" 4
.el .IP "\f(CW$self\fR\->verilog_text" 4
.IX Item "$self->verilog_text"
Returns verilog code which represents this modport. Returned as an array
that must be joined together to form the final text string. The netlist
must be already \->link'ed for this to work correctly.
.SH "DISTRIBUTION"
.IX Header "DISTRIBUTION"
Verilog-Perl is part of the free Verilog \s-1EDA\s0
software tool suite. The latest version is available from \s-1CPAN\s0 and from
.
.PP
Copyright 2000\-2020 by Wilson Snyder. This package is free software; you
can redistribute it and/or modify it under the terms of either the \s-1GNU\s0
Lesser General Public License Version 3 or the Perl Artistic License
Version 2.0.
.SH "AUTHORS"
.IX Header "AUTHORS"
Wilson Snyder
.SH "SEE ALSO"
.IX Header "SEE ALSO"
Verilog-Perl,
Verilog::Netlist::Subclass
Verilog::Netlist::Interface
Verilog::Netlist