Scroll to navigation



arachne-pnr - Place and route tool for iCE40 family FGPAs


arachne-pnr [options] <filename>


Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys synthesis suite for example. It currently targets the Lattice Semiconductor iCE40 family of FPGAs. Its output is a textual bitstream representation for assembly by the IceStorm icepack command. The output of icepack is a binary bitstream which can be uploaded to a hardware device.


Print this usage message.
Run quiet. Don't output progress messages.
Target device <device>. Supported devices: 1k - Lattice Semiconductor iCE40LP/HX1K 8k - Lattice Semiconductor iCE40LP/HX8K Default: 1k
Read chip database from <chipdb-file>. Default: /usr/share/arachne-pnr/chipdb-<device>.bin
Write binary chipdb to <file>.
Don't promote nets to globals.
Write post-pack netlist to <file> as BLIF.
Write post-pack netlist to <file> as Verilog.
Write post-place netlist to <file> as BLIF.
Input must include placement.
Read physical constraints from <pcf-file>.
Target package <package>. Default: tq144 for 1k, ct256 for 8k
Randomize seed.
Maximum number of routing passes. Default: 200
Set seed for random generator to <int>. Default: 1
Write pin assignments to <pcf-file> after placement.
Write output to <output-file>.


This manual page was written by Ruben Undheim <> for the Debian project (and may be used by others).

15 February 2021