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.\" ========================================================================
.\"
.IX Title "Netlist::Net 3pm"
.TH Netlist::Net 3pm "2022-10-20" "perl v5.36.0" "User Contributed Perl Documentation"
.\" For nroff, turn off justification.  Always turn off hyphenation; it makes
.\" way too many mistakes in technical documents.
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.nh
.SH "NAME"
Verilog::Netlist::Net \- Net for a Verilog Module
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
.Vb 1
\&  use Verilog::Netlist;
\&
\&  ...
\&  my $net = $module\->find_net(\*(Aqsignalname\*(Aq);
\&  print $net\->name;
.Ve
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
A Verilog::Netlist::Net object is created by Verilog::Netlist::Module for
every signal and input/output declaration, and parameter in the current
module.
.SH "ACCESSORS"
.IX Header "ACCESSORS"
See also Verilog::Netlist::Subclass for additional accessors and methods.
.ie n .IP "$self\->array" 4
.el .IP "\f(CW$self\fR\->array" 4
.IX Item "$self->array"
Any array (vector) declaration for the net.  This is for Verilog 2001
multidimensional signals; for the width of a signal, use msb/lsb/width. For
newer applications use \fBdata_type()\fR as it supports SystemVerilog types.
.ie n .IP "$self\->comment" 4
.el .IP "\f(CW$self\fR\->comment" 4
.IX Item "$self->comment"
Returns any comments following the definition.  keep_comments=>1 must be
passed to Verilog::Netlist::new for comments to be retained.
.ie n .IP "$self\->data_type" 4
.el .IP "\f(CW$self\fR\->data_type" 4
.IX Item "$self->data_type"
The data type of the net.  This may be a data type keyword (\*(L"integer\*(R",
\&\*(L"logic\*(R", etc), user defined type from a type def, a range (\*(L"[11:0]\*(R",
\&\*(L"signed [1:0]\*(R" or "" for an implicit wire.
.ie n .IP "$self\->decl_type" 4
.el .IP "\f(CW$self\fR\->decl_type" 4
.IX Item "$self->decl_type"
How the net was declared.  A declaration keyword (\*(L"genvar\*(R", \*(L"localparam\*(R",
\&\*(L"parameter\*(R", \*(L"var\*(R") or \*(L"port\*(R" if only as a port \- and see the port method,
or \*(L"net\*(R" \- and see the net_type method.
.ie n .IP "$self\->module" 4
.el .IP "\f(CW$self\fR\->module" 4
.IX Item "$self->module"
Reference to the Verilog::Netlist::Module or Verilog::Netlist::Interface
the net is under.
.ie n .IP "$self\->lsb" 4
.el .IP "\f(CW$self\fR\->lsb" 4
.IX Item "$self->lsb"
The least significant bit number of the net.
.ie n .IP "$self\->msb" 4
.el .IP "\f(CW$self\fR\->msb" 4
.IX Item "$self->msb"
The most significant bit number of the net.
.ie n .IP "$self\->name" 4
.el .IP "\f(CW$self\fR\->name" 4
.IX Item "$self->name"
The name of the net.
.ie n .IP "$self\->net_type" 4
.el .IP "\f(CW$self\fR\->net_type" 4
.IX Item "$self->net_type"
The net type, if one applies.  Always a net type keyword ('supply0',
\&'supply1', 'tri', 'tri0', 'tri1', 'triand', 'trior', 'trireg', 'wand',
\&'wire', 'wor').
.ie n .IP "$self\->type" 4
.el .IP "\f(CW$self\fR\->type" 4
.IX Item "$self->type"
The type function is provided for backward compatibility to Verilog-Perl
versions before 3.200. Applications should change to use \fBdata_type()\fR and/or
\&\fBdecl_type()\fR instead.
.Sp
The type function returns an agglomeration of data_type, net_type and
decl_type that worked ok in Verilog, but does not work with SystemVerilog.
Calls to \fBtype()\fR will be converted to calls to data_type, decl_type or
net_type in a way that attempts to maintain backward compatibility, however
compatibility is not always possible.
.ie n .IP "$self\->value" 4
.el .IP "\f(CW$self\fR\->value" 4
.IX Item "$self->value"
If the net's type is 'parameter', the value from the parameter's
declaration.
.ie n .IP "$self\->width" 4
.el .IP "\f(CW$self\fR\->width" 4
.IX Item "$self->width"
The width of the net in bits.
.SH "MEMBER FUNCTIONS"
.IX Header "MEMBER FUNCTIONS"
See also Verilog::Netlist::Subclass for additional accessors and methods.
.ie n .IP "$self\->lint" 4
.el .IP "\f(CW$self\fR\->lint" 4
.IX Item "$self->lint"
Checks the net for errors.  Normally called by Verilog::Netlist::lint.
.ie n .IP "$self\->dump" 4
.el .IP "\f(CW$self\fR\->dump" 4
.IX Item "$self->dump"
Prints debugging information for this net.
.ie n .IP "$self\->dump_drivers" 4
.el .IP "\f(CW$self\fR\->dump_drivers" 4
.IX Item "$self->dump_drivers"
Prints debugging information for this net, and all pins driving the net.
.SH "DISTRIBUTION"
.IX Header "DISTRIBUTION"
Verilog-Perl is part of the <https://www.veripool.org/> free Verilog \s-1EDA\s0
software tool suite.  The latest version is available from \s-1CPAN\s0 and from
<https://www.veripool.org/verilog\-perl>.
.PP
Copyright 2000\-2022 by Wilson Snyder.  This package is free software; you
can redistribute it and/or modify it under the terms of either the \s-1GNU\s0
Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
.SH "AUTHORS"
.IX Header "AUTHORS"
Wilson Snyder <wsnyder@wsnyder.org>
.SH "SEE ALSO"
.IX Header "SEE ALSO"
Verilog-Perl,
Verilog::Netlist::Subclass
Verilog::Netlist