.\" DO NOT MODIFY THIS FILE! It was generated by help2man 1.49.2. .TH CBFSTOOL: "8" "December 2022" "cbfstool: Management utility for CBFS formatted ROM images" "System Administration Utilities" .SH NAME cbfstool: \- manual page for cbfstool: Management utility for CBFS formatted ROM images .SH DESCRIPTION cbfstool: Management utility for CBFS formatted ROM images .SS "USAGE:" .IP debian/coreboot\-utils/usr/sbin/cbfstool [\-h] debian/coreboot\-utils/usr/sbin/cbfstool FILE COMMAND [\-v] [PARAMETERS]... .SS "OPTIONs:" .HP \fB\-H\fR header_offset Do not search for header; use this offset* .TP \fB\-T\fR Output top\-aligned memory address .TP \fB\-u\fR Accept short data; fill upward/from bottom .TP \fB\-d\fR Accept short data; fill downward/from top .TP \fB\-F\fR Force action .TP \fB\-g\fR Generate position and alignment arguments .TP \fB\-U\fR Unprocessed; don't decompress or make ELF .TP \fB\-v\fR Provide verbose output .TP \fB\-h\fR Display this help message .TP \fB\-\-ext\-win\-base\fR Base of extended decode window in host address space(x86 only) .TP \fB\-\-ext\-win\-size\fR Size of extended decode window in host address space(x86 only) .SS "COMMANDs:" .IP add [\-r image,regions] \fB\-f\fR FILE \fB\-n\fR NAME \fB\-t\fR TYPE [\-A hash] \e .IP [\-c compression] [\-b base\-address | \fB\-a\fR alignment] \e [\-p padding size] [\-y|\-\-xip if TYPE is FSP] \e [\-j topswap\-size] (Intel CPUs only) [\-\-ibb] \e [\-\-ext\-win\-base win\-base \fB\-\-ext\-win\-size\fR win\-size] Add a component .IP \fB\-j\fR valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 .IP add\-payload [\-r image,regions] \fB\-f\fR FILE \fB\-n\fR NAME [\-A hash] \e .IP [\-c compression] [\-b base\-address] \e (linux specific: [\-C cmdline] [\-I initrd]) Add a payload to the ROM .IP add\-stage [\-r image,regions] \fB\-f\fR FILE \fB\-n\fR NAME [\-A hash] \e .IP [\-c compression] [\-b base] [\-S section\-to\-ignore] \e [\-a alignment] [\-Q|\-\-pow2page] \e [\-y|\-\-xip] [\-\-ibb] \e [\-\-ext\-win\-base win\-base \fB\-\-ext\-win\-size\fR win\-size] Add a stage to the ROM .IP add\-flat\-binary [\-r image,regions] \fB\-f\fR FILE \fB\-n\fR NAME \e .IP [\-A hash] \fB\-l\fR load\-address \fB\-e\fR entry\-point \e [\-c compression] [\-b base] Add a 32bit flat mode binary .TP add\-int [\-r image,regions] \fB\-i\fR INTEGER \fB\-n\fR NAME [\-b base] Add a raw 64\-bit integer value .IP add\-master\-header [\-r image,regions] \e .TP [\-j topswap\-size] (Intel CPUs only) Add a legacy CBFS master header .TP remove [\-r image,regions] \fB\-n\fR NAME Remove a component .TP compact \fB\-r\fR image,regions Defragment CBFS image. .TP copy \fB\-r\fR image,regions \fB\-R\fR source\-region Create a copy (duplicate) cbfs instance in fmap .IP create \fB\-m\fR ARCH \fB\-s\fR size [\-b bootblock offset] \e .TP [\-o CBFS offset] [\-H header offset] [\-B bootblock] Create a legacy ROM file with CBFS master header* .TP create \fB\-M\fR flashmap [\-r list,of,regions,containing,cbfses] Create a new\-style partitioned firmware image .IP locate [\-r image,regions] \fB\-f\fR FILE \fB\-n\fR NAME [\-P page\-size] \e .TP [\-a align] [\-T] Find a place for a file of that size .TP layout [\-w] List mutable (or, with \fB\-w\fR, readable) image regions .TP print [\-r image,regions] [\-k] Show the contents of the ROM .TP extract [\-r image,regions] [\-m ARCH] \fB\-n\fR NAME \fB\-f\fR FILE [\-U] Extracts a file from ROM .TP write [\-F] \fB\-r\fR image,regions \fB\-f\fR file [\-u | \fB\-d]\fR [\-i int] Write file into same\-size [or larger] raw region .TP read [\-r fmap\-region] \fB\-f\fR file Extract raw region contents into binary file .TP truncate [\-r fmap\-region] Truncate CBFS and print new size on stdout .TP expand [\-r fmap\-region] Expand CBFS to span entire region .SS "OFFSETs:" .IP Numbers accompanying \fB\-b\fR, \fB\-H\fR, and \fB\-o\fR switches* may be provided in two possible formats: if their value is greater than 0x80000000, they are interpreted as a top\-aligned x86 memory address; otherwise, they are treated as an offset into flash. .SS "ARCHes:" .IP arm64, arm, mips, ppc64, power8, riscv, x86, unknown .SS "TYPEs:" .IP bootblock, cbfs header, stage, simple elf, fit, optionrom, bootsplash, raw, vsa, mbi, microcode, fsp, mrc, cmos_default, cmos_layout, spd, mrc_cache, mma, efi, struct, deleted, null .PP * Note that these actions and switches are only valid when .IP working with legacy images whose structure is described primarily by a CBFS master header. New\-style images, in contrast, exclusively make use of an FMAP to describe their layout: this must minimally contain an 'FMAP' section specifying the location of this FMAP itself and a 'COREBOOT' section describing the primary CBFS. It should also be noted that, when working with such images, the \fB\-F\fR and \fB\-r\fR switches default to 'COREBOOT' for convenience, and both the \fB\-b\fR switch to CBFS operations and the output of the locate action become relative to the selected CBFS region's lowest address. The one exception to this rule is the top\-aligned address, which is always relative to the end of the entire image rather than relative to the local region; this is true for for both input (sufficiently large) and output (\fB\-T\fR) data. .SS "USAGE:" .IP debian/coreboot\-utils/usr/sbin/cbfstool [\-h] debian/coreboot\-utils/usr/sbin/cbfstool FILE COMMAND [\-v] [PARAMETERS]... .SS "OPTIONs:" .HP \fB\-H\fR header_offset Do not search for header; use this offset* .TP \fB\-T\fR Output top\-aligned memory address .TP \fB\-u\fR Accept short data; fill upward/from bottom .TP \fB\-d\fR Accept short data; fill downward/from top .TP \fB\-F\fR Force action .TP \fB\-g\fR Generate position and alignment arguments .TP \fB\-U\fR Unprocessed; don't decompress or make ELF .TP \fB\-v\fR Provide verbose output .TP \fB\-h\fR Display this help message .TP \fB\-\-ext\-win\-base\fR Base of extended decode window in host address space(x86 only) .TP \fB\-\-ext\-win\-size\fR Size of extended decode window in host address space(x86 only) .SS "COMMANDs:" .IP add [\-r image,regions] \fB\-f\fR FILE \fB\-n\fR NAME \fB\-t\fR TYPE [\-A hash] \e .IP [\-c compression] [\-b base\-address | \fB\-a\fR alignment] \e [\-p padding size] [\-y|\-\-xip if TYPE is FSP] \e [\-j topswap\-size] (Intel CPUs only) [\-\-ibb] \e [\-\-ext\-win\-base win\-base \fB\-\-ext\-win\-size\fR win\-size] Add a component .IP \fB\-j\fR valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 .IP add\-payload [\-r image,regions] \fB\-f\fR FILE \fB\-n\fR NAME [\-A hash] \e .IP [\-c compression] [\-b base\-address] \e (linux specific: [\-C cmdline] [\-I initrd]) Add a payload to the ROM .IP add\-stage [\-r image,regions] \fB\-f\fR FILE \fB\-n\fR NAME [\-A hash] \e .IP [\-c compression] [\-b base] [\-S section\-to\-ignore] \e [\-a alignment] [\-Q|\-\-pow2page] \e [\-y|\-\-xip] [\-\-ibb] \e [\-\-ext\-win\-base win\-base \fB\-\-ext\-win\-size\fR win\-size] Add a stage to the ROM .IP add\-flat\-binary [\-r image,regions] \fB\-f\fR FILE \fB\-n\fR NAME \e .IP [\-A hash] \fB\-l\fR load\-address \fB\-e\fR entry\-point \e [\-c compression] [\-b base] Add a 32bit flat mode binary .TP add\-int [\-r image,regions] \fB\-i\fR INTEGER \fB\-n\fR NAME [\-b base] Add a raw 64\-bit integer value .IP add\-master\-header [\-r image,regions] \e .TP [\-j topswap\-size] (Intel CPUs only) Add a legacy CBFS master header .TP remove [\-r image,regions] \fB\-n\fR NAME Remove a component .TP compact \fB\-r\fR image,regions Defragment CBFS image. .TP copy \fB\-r\fR image,regions \fB\-R\fR source\-region Create a copy (duplicate) cbfs instance in fmap .IP create \fB\-m\fR ARCH \fB\-s\fR size [\-b bootblock offset] \e .TP [\-o CBFS offset] [\-H header offset] [\-B bootblock] Create a legacy ROM file with CBFS master header* .TP create \fB\-M\fR flashmap [\-r list,of,regions,containing,cbfses] Create a new\-style partitioned firmware image .IP locate [\-r image,regions] \fB\-f\fR FILE \fB\-n\fR NAME [\-P page\-size] \e .TP [\-a align] [\-T] Find a place for a file of that size .TP layout [\-w] List mutable (or, with \fB\-w\fR, readable) image regions .TP print [\-r image,regions] [\-k] Show the contents of the ROM .TP extract [\-r image,regions] [\-m ARCH] \fB\-n\fR NAME \fB\-f\fR FILE [\-U] Extracts a file from ROM .TP write [\-F] \fB\-r\fR image,regions \fB\-f\fR file [\-u | \fB\-d]\fR [\-i int] Write file into same\-size [or larger] raw region .TP read [\-r fmap\-region] \fB\-f\fR file Extract raw region contents into binary file .TP truncate [\-r fmap\-region] Truncate CBFS and print new size on stdout .TP expand [\-r fmap\-region] Expand CBFS to span entire region .SS "OFFSETs:" .IP Numbers accompanying \fB\-b\fR, \fB\-H\fR, and \fB\-o\fR switches* may be provided in two possible formats: if their value is greater than 0x80000000, they are interpreted as a top\-aligned x86 memory address; otherwise, they are treated as an offset into flash. .SS "ARCHes:" .IP arm64, arm, mips, ppc64, power8, riscv, x86, unknown .SS "TYPEs:" .IP bootblock, cbfs header, stage, simple elf, fit, optionrom, bootsplash, raw, vsa, mbi, microcode, fsp, mrc, cmos_default, cmos_layout, spd, mrc_cache, mma, efi, struct, deleted, null .PP * Note that these actions and switches are only valid when .IP working with legacy images whose structure is described primarily by a CBFS master header. New\-style images, in contrast, exclusively make use of an FMAP to describe their layout: this must minimally contain an 'FMAP' section specifying the location of this FMAP itself and a 'COREBOOT' section describing the primary CBFS. It should also be noted that, when working with such images, the \fB\-F\fR and \fB\-r\fR switches default to 'COREBOOT' for convenience, and both the \fB\-b\fR switch to CBFS operations and the output of the locate action become relative to the selected CBFS region's lowest address. The one exception to this rule is the top\-aligned address, which is always relative to the end of the entire image rather than relative to the local region; this is true for for both input (sufficiently large) and output (\fB\-T\fR) data.